參數(shù)資料
型號: HYB 39S256800T
廠商: SIEMENS AG
英文描述: 256-Mbit(4banks × 8MBit × 8) Synchronous DRAM(256M(4列 × 8M位 × 8)同步動態(tài)RAM)
中文描述: 256兆位(4banks × 8MBit × 8)同步DRAM(256M(4列× 8米× 8位)同步動態(tài)RAM)的
文件頁數(shù): 9/47頁
文件大小: 316K
代理商: HYB 39S256800T
HYB 39S256400/800/160T
256-MBit Synchronous DRAM
Data Book
9
12.99
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Notes
1.
V = Valid, x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock
before the commands are provided.
3. This is the state of the banks designated by BA0, BA1 signals.
4. Device state is Full Page Burst operation, which is not supported on this device.
5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode
cycle device is clock suspend mode.
Operation
Device
State
CKE
n-1
CKE
n
DQM
BA0
BA1
AP=
A10
Addr
.
CS
RAS
CAS
WE
Bank Active
Idle
3
H
X
X
V
V
V
L
L
H
H
Bank Precharge
Any
H
X
X
V
L
X
L
L
H
L
Precharge All
Any
H
X
X
X
H
X
L
L
H
L
Write
Active
3
H
X
X
V
L
V
L
H
L
L
Write with Autoprecharge
Active
3
H
X
X
V
H
V
L
H
L
L
Read
Active
3
H
X
X
V
L
V
L
H
L
H
Read with Autoprecharge
Active
3
H
X
X
V
H
V
L
H
L
H
Mode Register Set
Idle
H
X
X
V
V
V
L
L
L
L
No Operation
Any
H
X
X
X
X
X
L
H
H
H
Burst Stop
Active
4
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
Auto Refresh
Idle
H
H
X
X
X
X
L
L
L
H
Self Refresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
Self Refresh Exit
Idle
(Self
Refr.)
L
H
X
X
X
X
H
X
X
X
L
H
H
X
Clock Suspend Entry
Active
H
L
X
X
X
X
X
X
X
X
Power Down Entry
(Precharge or active
standby)
Idle
Active
5
H
L
X
X
X
X
H
X
X
X
L
H
H
X
Clock Suspend Exit
Active
L
H
X
X
X
X
X
X
X
X
Power Down Exit
Any
(Power
Down)
L
H
X
X
X
X
H
X
X
X
L
H
H
L
Data Write/Output Enable
Active
H
X
L
X
X
X
X
X
X
X
Data Write/Output Disable
Active
H
X
H
X
X
X
X
X
X
X
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