參數(shù)資料
型號： HYB18T1G160AFL-3
廠商： INFINEON TECHNOLOGIES AG
英文描述： 1 Gbit DDR2 SDRAM
中文描述： 1千兆位DDR2內(nèi)存
文件頁數(shù)： 83/89頁
文件大小： 1752K
代理商： HYB18T1G160AFL-3
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
INFINEON Technologies
Page 83 Rev. 1.02 May 2004
8.3.3 Slew Rate Definition for Input and Data Setup and Hold Times
Setup (tIS & tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VREF(dc) and the first crossing of VIH(ac)min. Setup (tIS & tDS) nominal slew rate for a falling signal is defined as
the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is
always earlier than the nominal slew rate line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for
derating value (see fig. A). If the actual signal is later than the nominal slew rate line anywhere between shaded
‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for
derating value.(see fig.B)
Hold (tIH & tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(dc)max and the first crossing of VREF(dc). Hold (tIH & tDH) nominal slew rate for a falling signal is defined as
the slew rate between the last crossing of VIH(dc)min and the first crossing of VREF(dc). If the actual signal is
always later than the nominal slew rate line between shaded ‘dc to VREF region’, use nominal slew rate for derat-
ing value (see fig. A). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to
VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF level is used for
derating value (see fig.B).
Setup Slew Rate =
VIL(dc)max - VIL(ac)max
VREF(dc) - VIL(ac)max
Delta TFS
falling signal
Setup Slew Rate =
VIH(dc)min - VIL(ac)min
VIH(ac)min - VREF(dc)
Delta TRS
rising signal
Hold Slew Rate =
VREF - VIL(dc)max
VREF(dc) - VIL(dc)max
Delta TRH
rising signal
Hold Slew Rate =
VIH(dc)min - VREF(dc)
Delta TFH
falling signal
Setup Slew Rate =
tangent line [VREF(dc) - VIL(ac)max]
Delta TFS
Setup Slew Rate =
tangent line [VIH(ac)min - VREF(dc)]
Delta TRS
Hold Slew Rate =
tangent line [VREF(dc) - VIL(dc)max]
Delta TRH
Hold Slew Rate =
tangent line [VIH(dc)min - VREF(dc)]
Delta TFH
falling
signal
falling
signal
rising
signal
rising
signal
fig. A
fig. B
V
SS
V
IL(ac)
max
V
IL(dc)
max
V
REF
V
IH(dc)
min
V
DDQ
V
IH(ac)
min
Delta TFS
Delta TRH
Delta TFH
Delta TRS
dc to VREF
region
VREF to ac
region
dc to VREF
region
VREF to ac
region
CK, CK for tIS and tIH
DQS, DQS for tDS and tDH
t
IS
t
DS
t
IH
t
DH
t
IS
t
DS
t
IH
t
DH
V
SS
V
IL(ac)
max
V
IL(dc)
max
V
REF
V
IH(dc)
min
V
DDQ
V
IH(ac)
min
Delta TFS
Delta TRH
Delta TFH
Delta TRS
dc to Vref
region
dc to Vref
region
VREF to ac
region
VREF to ac
region
tangent line
nominal line
CK, CK for tIS and tIH
DQS, DQS for tDS and tDH
t
IS
t
DS
t
IH
t
DH
t
IS
t
DS
t
IH
t
DH
相關(guān)PDF資料
PDF描述
HYB18T1G400AFL-37 1 Gbit DDR2 SDRAM
HYB18T1G160AFL-37 1 Gbit DDR2 SDRAM
HYB18T1G400AFL-3S 1 Gbit DDR2 SDRAM
HYB18T1G160AFL-3S 1 Gbit DDR2 SDRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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HYB18T1G400AF-5 制造商:Infineon Technologies AG 功能描述:256M X 4 DDR DRAM, 0.6 ns, PBGA68
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HYB18T256400AF-5 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA
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