參數(shù)資料
型號: HYB18T1G160AFL-3S
廠商: INFINEON TECHNOLOGIES AG
英文描述: 1 Gbit DDR2 SDRAM
中文描述: 1千兆位DDR2內(nèi)存
文件頁數(shù): 5/89頁
文件大?。?/td> 1752K
代理商: HYB18T1G160AFL-3S
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
INFINEON Technologies
Page 5 Rev. 1.02 May 2004
1.2.1 x8 Components
Symbol
1.2.3 x16 Components
Function
Symbol
Function
A0~A13
Row Address Inputs
DQS, DQS
Differential Data Strobes
A0~A9
Column Address Inputs
RDQS, RDQS
Differential Read Data Strobes
BA0, BA1, BA2
Bank Address Inputs
Column Address Input
for Auto-Precharge
Chip Select
VDD
Supply Voltage
A10/AP
VSS
Ground
CS
VDDQ
Supply Voltage for DQ
RAS
Row Address Strobe
VSSQ
Ground for DQs
CAS
Column Address Strobe
VDDL
Supply Voltage for DLL
WE
Write Enable
VSSDL
Ground for DLL
Reference Voltage for SSTL
Inputs
On Die Termination Enable
DQ0~DQ7
Data Inputs/Outputs (x8)
VREF
CKE
Clock Enable
ODT
CK, CK
Differential Clock Inputs
NC
Not connected
DM
Data Input Mask
Symbol
Function
Symbol
Function
A0~A12
Row Address Inputs
LDQS,LDQS
UDQS,UDQS
Differential Data Strobes
A0~A9
Column Address Inputs
NC
No Connection (Chip to Pin)
BA0, BA1, BA2
Bank Address Inputs
Column Address Input
for Auto-Precharge
Chip Select
VDD
Supply Voltage
A10/AP
VSS
Ground
CS
VDDQ
Supply Voltage for DQ
RAS
Row Address Strobe
VSSQ
Ground for DQs
CAS
Column Address Strobe
VDDL
Supply Voltage for DLL
WE
Write Enable
VSSDL
Ground for DLL
Reference Voltage for SSTL
Inputs
On Die Termination Enable
LDQ0~7, UDQ0~7
Data Inputs/Outputs
VREF
CKE
Clock Enable
ODT
CK, CK
Differential Clock Inputs
NC
Not connected
LDM, UDM
Data Input Masks
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