參數(shù)資料
型號(hào)： HYB18T1G400AFL-37
廠商： INFINEON TECHNOLOGIES AG
英文描述： 1 Gbit DDR2 SDRAM
中文描述： 1千兆位DDR2內(nèi)存
文件頁(yè)數(shù)： 64/89頁(yè)
文件大?。?/td> 1752K
代理商： HYB18T1G400AFL-37
Page 64 Rev. 1.02 May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
5. AC & DC Operating Conditions
5.1 DC Operating Conditions
5.1.1 Recommended DC Operating Conditions (SSTL_18)
5.1.2 ODT DC Electrical Characteristics
5.1.3 Input and Output Leakage Currents
:
Symbol
Parameter
Rating
Units
Notes
Min.
Typ.
Max.
VDD
Supply Voltage
1.7
1.8
1.9
V
1
VDDDL
Supply Voltage for DLL
1.7
1.8
1.9
V
1
VDDQ
Supply Voltage for Output
1.7
1.8
1.9
V
1
VREF
Input Reference Voltage
0.49 * VDDQ
0.5 * VDDQ
0.51 * VDDQ
V
2, 3
VTT
Termination Voltage
VREF - 0.04
VREF
VREF + 0.04
V
4
1. VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is
expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
3. Peak to peak ac noise on VREF may not exceed +/- 2% VREF (dc).
4. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF
and must track variations in die dc level of VREF.
Parameter / Condition
Symbol
min.
nom.
max.
Units
Notes
Rtt(eff) impedance value for EMRS(1)(A6,A2)=0,1; 75 ohm
Rtt1(eff)
60
75
90
1
Rtt(eff) impedance value for EMRS(1)(A6,A2)=1,0; 150 ohm
Rtt2(eff)
120
150
180
1
Deviation of VM with respect to VDDQ / 2
delta VM
- 6.00
+ 6.00
%
2
1) Measurement Definition for Rtt(eff):
Apply VIH(ac) and VIL(ac) to test pin separately, then measure current
Ι
(VIHac) and
Ι
(VILac) respectively.
Rtt(eff) = (VIH(ac) - VIL(ac)) /(
Ι
(VIHac) -
Ι
(VILac))
2) Measurement Definition for VM:
Measure voltage (VM) at test pin (midpoint) with no load:
delta VM =((2* VM / VDDQ) - 1) x 100%
Symbol
Parameter / Condition
min.
max.
Units
Notes
IIL
Input Leakage Current; any input 0V < VIN < VDD
-2
+2
μΑ
1
IOL
Output Leakage Current; 0V < VOUT < VDDQ
-5
+5
μΑ
2
notes: 1) all other pins not under test = 0V
2) DQ’s, DQS, DQS and ODT are disabled
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