參數(shù)資料
型號(hào)： HYB18T1G400AFL-37
廠商： INFINEON TECHNOLOGIES AG
英文描述： 1 Gbit DDR2 SDRAM
中文描述： 1千兆位DDR2內(nèi)存
文件頁數(shù)： 84/89頁
文件大小： 1752K
代理商： HYB18T1G400AFL-37
Page 84 Rev. 1.02 May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
8.3.4 Input Setup (tIS) and Hold (tIH) Time Derating Table
8.3.5 Data Setup (tDS) and Hold Time (tDH) Derating Tablefor differential DQS / DQS
CK, CK Differential Slew Rate
1.5 V/ns
tIS
+217
+209
+197
+180
+155
+113
+30
+19
+5
-13
-37
-80
-145
-255
-320
-495
-770
-1420
2.0 V/ns
1.0 V/ns
tIS
+187
+179
+167
+150
+125
+83
0
-11
-25
-43
-67
-110
-175
-285
-350
-525
-800
-1450
tIH
+94
+89
+83
+75
+45
+21
0
-14
-31
-54
-83
-125
-188
-292
-375
-500
-708
-1125
tIH
+124
+119
+113
+105
+75
+51
+30
+16
-1
-24
-53
-95
-158
-262
-345
-470
-678
-1095
tIS
+247
+239
+227
+210
+185
+143
+60
+49
+35
+17
-7
-50
-115
-225
-290
-465
-740
-1390
tIH
+154
+149
+143
+135
+105
+81
+60
+46
+29
+6
-23
-65
-128
-232
-315
-440
-648
-1065
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
C
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
1. For all input signals the total tIS (input setup time) and tIH (input hold time) required is calculated by adding the individual
datasheet value to the derating value listed in the previous table.
2. For slow slewrate the total setup time might be negativ (i.e. a valid input signal will not have reached VIH(ac) / VIL(ac) at the
time of the rising clock) a valid input signal is still required to complete the transistion and reach VIH(ac) / VIL(ac). For slew
rates in between the values listed in the next tables, the derating values may be obtained by linear interpolation. These val-
ues are not subject to production test. They are verified only by design and characterisation.
DQS, DQS Differential Slew Rate
1.8 V/ns
1.6 V/ns
4.0 V/ns
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
Unit
2.0
+125 +45 +125 +45 +125 +45
-
-
-
1.5
+83
+21
+83
+21
+83
+21
+95
+33
-
1.0
0
0
0
0
0
0
+12
+12
+24
0.9
-
-
-11
-14
-11
-14
+1
-2
+13
0.8
-
-
-
-
-25
-31
-13
-19
-1
0.7
-
-
-
-
-
-
-31
-42
-19
0.6
-
-
-
-
-
-
-
-
-43
0.5
-
-
-
-
-
-
-
-
-
0.4
-
-
-
-
-
-
-
-
-
1. For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the individual datasheet value to the der-
ating value listed in the previous table.
3.0 V/ns
2.0 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
0.8 V/ns
D
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ps
ps
ps
ps
ps
ps
ps
ps
ps
+24
+10
-7
-30
-49
-
-
+25
+11
-7
-31
-74
-
+22
+5
-18
-47
-89
-
+23
+5
-19
-62
-127 -140 -115 -128 -103 -116
+17
-6
-35
-77
+17
-7
-50
+6
-23
-65
+5
-38
-11
-53
2. For slow slewrate the total setup time might be negativ (i.e. a valid input signal will not have reached VIH(ac) / VIL(ac) at the time of the ris-
ing DQS) a valid input signal is still required to complete the transistion and reach VIH(ac) / VIL(ac). For slew rates in between the values
listed in the next tables, the derating values may be obtained by linear interpolation. These values are not subject to production test. They
are verified only by design and characterisation.
相關(guān)PDF資料
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