參數(shù)資料
型號(hào)： HYB18T1G800AF-3
廠商： INFINEON TECHNOLOGIES AG
英文描述： 1 Gbit DDR2 SDRAM
中文描述： 1千兆位DDR2內(nèi)存
文件頁(yè)數(shù)： 21/89頁(yè)
文件大?。?/td> 1752K
代理商： HYB18T1G800AF-3
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
INFINEON Technologies
Page 21 Rev. 1.02 May 2004
Extended Mode Register Set for OCD impedance adjustment
OCD impedance adjustment can be done using the following EMRS(1) mode. In drive mode all outputs are driven
out by DDR2 SDRAM and drive of RDQS is dependent on EMRS(1) bit enabling RDQS operation. In Drive(1)
mode, all DQ, DQS (and RDQS) signals are driven high and all DQS (and RDQS) signals are driven low. In
Drive(0) mode, all DQ, DQS (and RDQS) signals are driven low and all DQS (and RDQS) signals are driven
high. In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver
characteristics have a nominal impedance value of 18 Ohms during nominal temperature and voltage conditions.
Output driver characteristics for OCD calibration default are specified in the following table. OCD applies only to
normal full strength output drive setting defined by EMRS(1) and if half strength is set, OCD default driver charac-
teristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics
are not applicable. After OCD calibration is completed or driver strength is set to default, subsequent EMRS(1)
commands not intended to adjust OCD characteristics must specify A7~A9 as’000’ in order to maintain the default
or calibrated value.
Off- Chip-Driver program
OCD impedance adjust
To adjust output driver impedance, controllers must issue the ADJUST EMRS(1) command along with a 4 bit
burst code to DDR2 SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via
MRS command before activating OCD and controllers must drive the burst code to all DQs at the same time. DT0
in the table means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted
for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a given DDR2 SDRAM will be
adjusted to the same driver strength setting. The maximum step count for adjustment is 16 and when the limit is
reached, further increment or decrement code has no effect. The default setting may be any step within the maxi-
mum step count range. When Adjust mode command is issued, AL from previously set value must be applied.
Off- Chip-Driver Adjust Program
A9
0
0
0
1
1
A8
0
0
1
0
1
A7
0
1
0
0
1
Operation
OCD calibration mode exit
Drive(1) DQ, DQS, (RDQS) high and DQS, (RDQS) low
Drive(0) DQ, DQS, (RDQS) low and DQS, (RDQS) high
Adjust mode
OCD calibration default
4 bit burst code inputs to all DQs
DT0
DT1
0
0
0
0
0
0
0
1
1
0
0
1
0
1
1
0
1
0
Other Combinations
Operation
DT2
0
0
1
0
0
0
1
0
1
DT3
0
1
0
0
0
1
0
1
0
Pull-up driver strength
NOP (no operation)
Pull-down driver strength
NOP (no operation)
Increase by 1 step
NOP
Decrease by 1 step
NOP
NOP
Increase by 1 step
NOP
Decrease by 1 step
Increase by 1 step
Increase by 1 step
Decrease by 1 step
Increase by 1 step
Increase by 1 step
Decrease by 1 step
Decrease by 1 step
Decrease by 1 step
Reserved
Reserved
相關(guān)PDF資料
PDF描述
HYB18T1G800AF-37 1 Gbit DDR2 SDRAM
HYB18T1G800AF-3S POT 1.0K OHM 1/4 SQ CERM SL ST
HYB18T1G800AF-5 1 Gbit DDR2 SDRAM
HYB18T1G800AFL-3 1 Gbit DDR2 SDRAM
HYB18T1G800AFL-37 1 Gbit DDR2 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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HYB18T256800AF-5 制造商:Infineon Technologies AG 功能描述:
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