參數(shù)資料
型號(hào): HYB314100BJL-50
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 4M x 1-Bit Dynamic RAM Low Power 4M x 1-Bit Dynamic RAM
中文描述: 4M X 1 FAST PAGE DRAM, 50 ns, PDSO20
封裝: 0.300 INCH, PLASTIC, SOJ-20
文件頁數(shù): 8/23頁
文件大?。?/td> 1153K
代理商: HYB314100BJL-50
Semiconductor Group
8
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
Output buffer turn-off delay
t
OFF
0
13
0
15
0
20
ns
12
Write Cycle
Write command hold time
t
WCH
t
WP
t
WCS
8
10
10
ns
Write command pulse width
8
10
10
ns
Write command setup time
Write command to RAS lead time
t
RWL
Write command to CAS lead time
t
CWL
Data setup time
0
0
0
ns
13
13
15
20
ns
13
15
20
ns
t
DS
t
DH
0
0
0
ns
14
Data hold time
10
10
15
ns
14
Read-Modify-Write Cycle
Read-write cycle time
t
RWC
t
RWD
t
CWD
t
AWD
115
130
155
ns
RAS to WE delay time
50
60
70
ns
13
CAS to WE delay time
13
15
20
ns
13
Column address to WE delay
time
25
30
35
ns
13
Fast Page Mode Cycle
Fast page mode cycle time
t
PC
t
CP
t
CPA
35
40
45
ns
CAS precharge time
10
10
10
ns
Access time from CAS
precharge
30
35
40
ns
7
RAS pulse width
t
RAS
t
RHCP
50
200 k 60
200 k 70
200 k ns
CAS precharge to RAS Delay
30
35
40
ns
AC Characteristics
(cont’d)
5)6)
T
A
= 0 to 70 C,
V
CC
= 3.3 V
±
0.3 V,
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
-70
min.
max. min.
max. min.
max.
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