參數(shù)資料
型號(hào)： HYB314265BJ-45
廠商： SIEMENS A G
元件分類： DRAM
英文描述： 256K x 16-Bit EDO-Dynamic RAM
中文描述： 256K X 16 EDO DRAM, 45 ns, PDSO40
文件頁(yè)數(shù)： 14/28頁(yè)
文件大?。?/td> 1324K
代理商： HYB314265BJ-45
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
14
7)
V
I
H
(min.)
and
V
I
L (max.)
are reference levels for measuring timing of input signals. Transition times are also
measured between
V
I
H
and
V
I
L
.
8) Measured with the specified current load and 50 pF at
V
OL
= 0.8 V and
V
OH
= 2.0 V. Access time is determined
by the latter of
t
RAC
,
t
CAC
,
t
AA
,
t
CPA
,
t
OEA
.
t
CAC
is measured from tristate
.
9) Operation within the
t
RCD (max.)
limit ensures that
t
RAC (max.)
can be met.
t
RCD (max.)
is specified as a reference point
only. If
t
RCD
is greater than the specified
t
RCD (max.)
limit, then access time is controlled by
t
CAC
.
10) Operation within the
t
RAD (max.
)
limit ensures that
t
RAC (max.)
can be met.
t
RAD (max.)
is specified as a reference point
only. If
t
RAD
is greater than the specified
t
RAD (max.)
limit, then access time is controlled by
t
AA
.
11) Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
12)
t
,
t
define the time at which the output achieves the open-circuit conditions and are not
referenced to output voltage levels.
t
OFF
is referenced from the rising edge of RAS or CAS, whichever occurs
last.
13) Either
t
DZC
or
t
DZO
must be satisfied.
14) Either
t
CDD
or
t
ODD
must be satisfied.
15)
t
WCS
,
t
RWD
,
t
CWD
and
t
AWD
are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If
t
>
t
, the cycle is an early write cycle and data out pin will remain
open-circuit (high impedance) through the entire cycle; if
t
RWD
>
t
RWD (min.)
,
t
CWD
>
t
CWD (min.)
and
t
AWD
>
t
AWD (min.)
,
the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above
sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.
16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR
refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the
refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately
after exit from Self Refresh.
50 pF
I/O
Z=50 Ohm
+ 1.5 V
50 Ohm
fig.2
相關(guān)PDF資料
PDF描述
HYB514265BJ-50 256K x 16-Bit EDO-Dynamic RAM
HYB314265BJ-50 256K x 16-Bit EDO-Dynamic RAM
HYB314265BJL-45 256K x 16-Bit EDO-Dynamic RAM
HYB314265BJL-50 256K x 16-Bit EDO-Dynamic RAM
HYB514405BJ-70 1M x 4-Bit Dynamic RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB314265BJ-50 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256K x 16-Bit EDO-Dynamic RAM
HYB314265BJL-45 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256K x 16-Bit EDO-Dynamic RAM
HYB314265BJL-50 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256K x 16-Bit EDO-Dynamic RAM
HYB314400BJ-50 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 4-Bit Dynamic RAM
HYB314400BJ-50- 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 4-Bit Dynamic RAM
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