參數(shù)資料
型號(hào): HYB314400BJ-60
廠商: SIEMENS A G
元件分類(lèi): DRAM
英文描述: IC-DARLINGTON ARRAY 4UNIT RoHS Compliant: Yes
中文描述: 1M X 4 FAST PAGE DRAM, 60 ns, PDSO20
封裝: 0.300 INCH, PLASTIC, SOJ-26
文件頁(yè)數(shù): 7/25頁(yè)
文件大?。?/td> 126K
代理商: HYB314400BJ-60
HYB 314400BJ-50/-60
3.3 V 1M
×
4 DRAM
Semiconductor Group
7
1998-10-01
AC Characteristics
T
A
= 0 to 70
°
C,
V
CC
= 3.3 V
±
0.3 V,
t
T
= 5 ns
Parameter
5, 6
Symbol
Limit Values
Unit Note
-50
-60
min.
max. min.
max.
Common Parameters
Random read or write cycle time
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
T
t
REF
95
110
ns
RAS precharge time
35
40
ns
RAS pulse width
50
10k
60
10k
ns
CAS pulse width
13
10k
15
10k
ns
Row address setup time
0
0
ns
Row address hold time
8
10
ns
Column address setup time
0
0
ns
Column address hold time
10
15
ns
RAS to CAS delay time
18
37
20
45
RAS to column address delay time
13
25
15
30
ns
RAS hold time
13
15
ns
CAS hold time
50
60
ns
CAS to RAS precharge time
5
5
ns
Transition time (rise and fall)
3
50
3
50
ns
7
Refresh period
16
16
ms
Read Cycle
Access time from RAS
t
RAC
t
CAC
t
AA
t
OEA
t
RAL
t
RCS
t
RCH
t
RRH
t
CLZ
t
OFF
t
OEZ
50
60
ns
8, 9
Access time from CAS
13
15
ns
8, 9
Access time from column address
25
30
ns
8, 10
OE access time
13
15
ns
Column address to RAS lead time
25
30
ns
Read command setup time
0
0
ns
Read command hold time
0
0
ns
11
Read command hold time referenced to RAS
0
0
ns
11
CAS to output in low-Z
0
0
ns
8
Output buffer turn-off delay
0
13
0
15
ns
12
Output buffer turn-off delay from OE
0
13
0
15
ns
12
相關(guān)PDF資料
PDF描述
HYB 314400BJ-60 1M × 4-Bit Dynamic RAM(Fast Page Mode)(1M x 4位 動(dòng)態(tài) RAM(快速頁(yè)面模式))
HYB 39S128160CT 128-Mbit(4banks × 2MBit × 16) Synchronous DRAM(128M(4列 × 2M位 × 16)同步動(dòng)態(tài)RAM)
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