參數(shù)資料
型號(hào): HYB39S128400CT-7.5
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128-MBit Synchronous DRAM
中文描述: 128兆位同步DRAM
文件頁(yè)數(shù): 2/51頁(yè)
文件大?。?/td> 470K
代理商: HYB39S128400CT-7.5
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies
2
9.01
Pin Definitions and Functions
Ordering Information
Type
Function Code
Package
Description
HYB 39S128400CT-7
PC133-222-520
P-TSOP-54 (400mil)
143MHz 4B
×
8M x4 SDRAM
HYB 39S128400CT-7.5
PC133-333-520
P-TSOP-54 (400mil)
133 MHz 4B
×
8M x4 SDRAM
HYB 39S128400CT-8
PC100-222-620
P-TSOP-54 (400mil)
100 MHz 4B
×
8M x4 SDRAM
HYB 39S128800CT-7
PC133-222-520
P-TSOP-54 (400mil)
143 MHz 4B
×
4M x8 SDRAM
HYB 39S128800CT-7.5
PC133-333-520
P-TSOP-54 (400mil)
133 MHz 4B
×
4M x8 SDRAM
HYB 39S128800CT-8
PC100-222-620
P-TSOP-54 (400mil)
100 MHz 4B
×
4M x8 SDRAM
HYB 39S128160CT-7
PC133-222-520
P-TSOP-54 (400mil)
143 MHz 4B
×
2M x16 SDRAM
HYB 39S128160CT-7.5
PC133-333-520
P-TSOP-54 (400mil)
133 MHz 4B
×
2M x16 SDRAM
HYB 39S128160CT-8
PC100-222-620
P-TSOP-54 (400mil)
100 MHz 4B
×
2M x16 SDRAM
HYB 39S128160CTL-8
PC100-222-620
P-TSOP-54 (400mil)
100 MHz 4B
×
2M x16 SDRAM
Low Power (
L
) version
HYB 39S128160CTL-7.5
PC133-333-520
P-TSOP-54 (400mil)
133 MHz 4B
×
2M x16 SDRAM
Low Power (
L
) version
CLK
Clock Input
DQ
Data Input/Output
CKE
Clock Enable
DQM, LDQM,
UDQM
V
DD
V
SS
V
DDQ
V
SSQ
N.C.
Data Mask
CS
Chip Select
Power (+ 3.3 V)
RAS
Row Address Strobe
Ground
CAS
Column Address Strobe
Power for DQ
s (+ 3.3 V)
WE
Write Enable
Ground for DQ
s
A0 - A11
Address Inputs
Not connected
BA0, BA1
Bank Select
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