參數(shù)資料
型號(hào): HYB39S128400CT-7.5
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128-MBit Synchronous DRAM
中文描述: 128兆位同步DRAM
文件頁(yè)數(shù): 26/51頁(yè)
文件大?。?/td> 470K
代理商: HYB39S128400CT-7.5
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies
27
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by a Read
1 Clk Interval
SPT03791
CLK
T0
T1
T2
T3
T4
T5
T6
T7
T8
Command
NOP
NOP
NOP
NOP
NOP
NOP
DQ’s
(Burst Length = 4, CAS latency = 2, 3)
NOP
Write A
DIN A0
DIN B0
DIN B1
DIN B2
DIN B3
Write B
1 Clk Interval
T5
NOP
DOUT B1
DOUT B0
Input data for the Write is ignored.
, DQ’s
latency = 3
t
CK3
CAS
don’t care
DIN A0
don’t care
(Burst Length = 4, CAS latency = 2, 3)
CLK
, DQ’s
Command
latency = 2
t
CK2
CAS
NOP
T0
DIN A0
Write A
don’t care
Read B
T1
T2
DOUT B0
NOP
NOP
T4
T3
SPT03719
appears on the outputs to avoid data contention.
DOUT B2
Input data must be removed from the DQ’s
at least one clock cycle before the Read data
DOUT B1
DOUT B3
NOP
DOUT B3
NOP
DOUT B2
T6
T7
NOP
T8
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