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參數(shù)資料
| 型號： | HYB39S16160AT-10 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | Multipole Connector |
| 中文描述： | 1M X 16 SYNCHRONOUS DRAM, 10 ns, PDSO50 |
| 封裝： | 0.400 INCH, TSSOP2-50 |
| 文件頁數(shù)： | 18/22頁 |
| 文件大?。?/td> | 147K |
| 代理商： | HYB39S16160AT-10 |
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
18
1998-10-01
Notes
1.
2.
V
IH
may overshoot to
V
CC
+ 2.0 V for pulse width of < 4 ns with 3.3 V.
V
IL
may undershoot to
– 2.0 V for pulse width < 4.0 ns with 3.3 V. Pulse width measured at 50 % points with amplitude
measured peak to DC reference.
3.
Under all conditions
V
DDQ
must be less than or equal to
V
DD
.
4.
The value of
V
REF
may be selected by the user to provide optimum noise margin in the system.
V
REF
has to be in the range between 0.43
×
V
DDQ
and 0.47
×
V
DDQ
and is expected to track
variations in
V
DDQ
.
5.
V
IH
may overshoot to
V
DD
,
V
DDQ
+ 1.2 V for pulse width < 5 ns and
V
IL
may undershoot to
V
SS
,
V
SSQ
– 1.2 V for pulse width < 5 ns.
6.
The specified values are valid when addresses are changed no more than three times during
t
RC(MIN.)
and when No Operation commands are registered on every rising clock edge during
t
RC(MIN.)
.
7.
The specified values are valid when data inputs (DQ’s) are stable during
t
RC(MIN.)
.
8.
An initial pause of 200
μ
s is required after power-up, then a Precharge All Banks command
must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set
Operation can begin.
9.
AC timing tests for LV-TTL versions have
V
IL
= 0.4 V and
V
IH
= 2.4 V with the timing referenced
to the 1.4 V crossover point. The transition time is measured between
V
IH
and
V
IL
. All AC
measurements assume
t
T
= 1 ns with the AC output load circuit shown in figure below.
10. If clock rising time is longer than 1 ns, (
t
T
/2 – 0.5) ns has to be added to this parameter.
11. If
t
T
is longer than 1 ns, a time (
t
T
– 1) ns has to be added to this parameter.
12. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up” the device.
13. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to
t
RC
is satisfied
once the Self Refresh Exit command is registered.
14. Referenced to the time which the output achieves the open circuit condition, not to output
voltage levels.
All voltages are referenced to
V
SS
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB39S16160AT-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
| HYB39S16160BT-10 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
| HYB39S16160BT-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
| HYB39S16160CT-10 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
| HYB39S16160CT6 | 制造商:SIEMENS 功能描述:New |
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