參數(shù)資料
型號(hào)： HYB39S16160AT-10
廠商： SIEMENS A G
元件分類： DRAM
英文描述： Multipole Connector
中文描述： 1M X 16 SYNCHRONOUS DRAM, 10 ns, PDSO50
封裝： 0.400 INCH, TSSOP2-50
文件頁(yè)數(shù)： 4/22頁(yè)
文件大?。?/td> 147K
代理商： HYB39S16160AT-10
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
4
1998-10-01
Signal Pin Description
Pin
Type
Signal Polarity Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are
sampled on the rising edge of the clock.
CKE
Input
Level
Active
High
Activates the CLK signal when high and deactivates the
CLK signal when low, thereby initiates either the Power
Down mode, Suspend mode or the Self Refresh mode.
CS
Input
Pulse
Active
Low
CS enables the command decoder when low and disables
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
RAS
CAS
WE
Input
Pulse
Active
Low
When sampled at the positive rising edge of the clock,
CAS, RAS and WE define the command to be executed by
the SDRAM.
A0 - A10
Input
Level
–
During a Bank Activate command cycle, A0 - A10 defines
the row address (RA0 - RA10) when sampled at the rising
clock edge.
During a Read or Write command cycle, A0 - A9 defines
the column address (CA0 - CAn) when sampled at the
rising clock edge. CAn depends from the SDRAM
organisation.
4M
×
4 SDRAM CAn = CA9
2M
×
8 SDRAM CAn = CA8
1M
×
16 SDRAM CAn = CA7
In addition to the column address, A10 is used to invoke
autoprecharge operation at the end of the burst read or
write cycle. If A10 is high, autoprecharge is selected and
A11 defines the bank to be precharged (low = bank A,
high = bank B). If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 is used in
conjunction with A11 to control which bank(s) to
precharge. If A10 is high, both bank A and bank B will be
precharged regardless of the state of A11. If A10 is low,
then A11 is used to define which bank to precharge.
A11 (BS)
Input
Level
–
Selects which bank is to be active. A11 low selects bank A
and A11 high selects bank B.
DQx
Input
Output
Level
–
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
相關(guān)PDF資料
PDF描述
HYB39S16160CT-6 1M x 16 MBit Synchronous DRAM for High Speed Graphics Applications
HYB39S16160CT-7 1M x 16 MBit Synchronous DRAM for High Speed Graphics Applications
HYB39S16160CT-8 16 MBit Synchronous DRAM
HYB39S16160BT-10 SWITCH, SPST
HYB39S16160CT-10 16 MBit Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB39S16160AT-8 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM
HYB39S16160BT-10 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM
HYB39S16160BT-8 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM
HYB39S16160CT-10 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM
HYB39S16160CT6 制造商:SIEMENS 功能描述:New
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