參數(shù)資料
型號: HYB39S16160CT-8
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 16 MBit Synchronous DRAM
中文描述: 1M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO50
封裝: 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP-50
文件頁數(shù): 20/22頁
文件大?。?/td> 147K
代理商: HYB39S16160CT-8
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
20
1998-10-01
Clock Frequency and Latency
Parameter
Symbol
Speed Sort
Unit
-8
-10
Clock frequency
max.
t
CK
min.
125
83
100
66
MHz
Clock Cycle time
t
CK
t
AA
t
RCD
t
RL
t
RAS
8
12
10
15
ns
CAS latency
min.
3
2
3
2
CLK
Row to Column delay
min.
3
2
3
2
CLK
RAS latency
min.
6
4
6
4
CLK
Row Active time
min.
max.
t
RAS
min.
5
3
5
3
CLK
μ
s
CLK
120
120
120
120
Row Precharge time
t
RP
t
RC
t
DPL
t
DPL
+
t
RP
5
t
RRD
t
CCD
3
2
3
2
Row Cycle time
min.
8
5
8
5
CLK
Last Data-In to Precharge (Write Recovery)
min.
2
1
2
1
CLK
Last Data-In to Active/Refresh
min.
3
5
3
CLK
Bank to Bank delay time
min.
2
2
2
2
CLK
CAS to CAS delay time
min.
fixed
t
WL
fixed
t
DQW
fixed
t
DQZ
fixed
t
CSL
1
1
1
1
CLK
Write latency
0
0
0
0
CLK
DQM Write Mask latency
0
0
0
0
CLK
DQM Data Disable latency
2
2
2
2
CLK
Clock Suspend latency
1
1
1
1
CLK
相關(guān)PDF資料
PDF描述
HYB39S16160BT-10 SWITCH, SPST
HYB39S16160CT-10 16 MBit Synchronous DRAM
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HYB39S16320TQ-7 128 x 64 pixel format, LED Backlight available
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