參數(shù)資料
型號： HYB39S16320TQ-7
廠商： SIEMENS A G
元件分類： DRAM
英文描述： 128 x 64 pixel format, LED Backlight available
中文描述： 512K X 32 SYNCHRONOUS GRAPHICS RAM, 5.5 ns, PQFP100
封裝： TQFP-100
文件頁數(shù)： 9/70頁
文件大?。?/td> 563K
代理商： HYB39S16320TQ-7
HYB 39S16320TQ-6/-7/-8
Semiconductor Group
9
1998-10-01
Mode Register Programming
The Mode Register is used to define: a Burst Length, a Burst type, a Read Latency and an operating
mode. The mode register is programmed via the Load Mode Register command and will retain the
stored information until it is programmed again or the device looses power. The mode register must
be loaded when both banks are idle and the controller must wait the specified time before initiating
the subsequent command. Violating either of these requirements may result in unknown operation.
Burst Length
Read and Write operations to the SGRAM are burst oriented, with the burst length being
programmable. The burst length determines the maximum number of column locations that can be
accessed for a given Read or Write command. Burst lengths of 1, 2, 4, or 8 locations are available
for both the sequential and the interleaved burst types and a Full Page Burst is available for the
sequential type. The Full Page Burst is used in conjunction with the Burst Terminate command to
generate arbitrary burst lengths.
When a Read or Write command is issued, a block of columns equal to the burst length is selected.
The block is defined by address bits A7 - A1 when the burst length is set to 2, by A7-A2 for burst
length set to 4 and by A7 - A3 for burst length set to 8. The lower order bit(s) are used to select the
starting location within the block. The burst will wrap within the block if a boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved and the
type is selected based on the setting of BT bit in the mode register. If BT is set to “0”, the burst type
is sequential, if BT is “1”, the burst type is interleave.
Read Latency
The Read Latency is the delay in clock cycles between the registration of a Read command and the
availability of the first piece of output data. The latency can be set to 2 or 3 clocks. If a Read
command is registered at clock edge n and the Read Latency is 2 clocks, the data will be available
by clock edge n + 2. The DQs will start driving already one cycle earlier (n + 1).
Color Register
The Siemens 16M SGRAM offers two Color Registers. If Bit M7 is set to “1”, two Color Register
mode is specified.
Operation Mode
In normal operation, the bits M8 and M9 of Mode Register (MR) are set “0”. The programmed burst
length applies to both read and write bursts. When bit M8 is set to “1”, burst read and single write
mode is selected.
Test modes and reserved states should not be used because unknown operation or incompatibility
with future versions may result.
相關(guān)PDF資料
PDF描述
HYB39S16320TQ-8 128 x 64 pixel format, LED Backlight available
HYB39S13620TQ- 128 x 64 pixel format, LED Backlight available
HYB39S16320TQ-10 128 x 64 pixel format, LED Backlight available
HYB39S16400-1 16 MBit Synchronous DRAM
HYB39S16400CT-8 16 MBit Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB39S16320TQ-8 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Special Mode Registers Two color registers Burst Read with Single Write Operation
HYB39S1632TQ55 制造商:N/A 功能描述:NEW
HYB39S16400 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM
HYB39S16400-1 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM
HYB39S16400AT-10 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM
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