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參數(shù)資料
| 型號： | HYB39S16400-1 |
| 廠商： | SIEMENS AG |
| 英文描述： | 16 MBit Synchronous DRAM |
| 中文描述： | 16兆位同步DRAM |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 101K |
| 代理商： | HYB39S16400-1 |
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
4
1998-10-01
Signal Pin Description
Pin
Type
Signal Polarity Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on
the rising edge of the clock.
CKE
Input
Level
Active
High
Activates the CLK signal when high and deactivates the CLK
signal when low, thereby inititiates either the Power Down mode,
Suspend mode or the Self Refresh mode.
CS
Input
Pulse
Active
Low
CS enables the command decoder when low and disables the
command decoder when high. When the command decoder is
disabled, new commands are ignored but previous operations
continue.
RAS
CAS
WE
Input
Pulse
Active
Low
When sampled at the positive rising edge of the clock, CAS,
RAS, and WE define the command to be executed by the
SDRAM.
A0 -
A10
Input
Level
–
During a Bank Activate command cycle, A0 - A10 defines the
row address (RA0 - RA10) when sampled at the rising clock
edge.
During a Read or Write command cycle, A0 - A9 defines the
column address (CA0 - CAn) when sampled at the rising clock
edge. CAn depends from the SDRAM organisation.
4M
×
4 SDRAM CAn = CA9
2M
×
8 SDRAM CAn = CA8
1M
×
16 SDRAM CAn = CA7
In addition to the column address, A10 is used to invoke auto-
precharge operation at the end of the burst read or write cycle. If
A10 is high, autoprecharge is selected and A11 defines the bank
to be precharged (low = bank A, high = bank B). If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction
with A11 to control which bank(s) to precharge. If A10 is high,
both bank A and bank B will be precharged regardless of the
state of A11. If A10 is low, then A11 is used to define which bank
to precharge.
A11
(BS)
Input
Level
–
Selects which bank is to be active. A11 low selects bank A and
A11 high selects bank B.
DQx
Input
Output
Level
–
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
DQM,
LDQM,
UDQM
Input
Pulse
Active
High
The Data Input/Output mask places the DQ buffers in a high
impedance state when sampled high. In Read mode, DQM has
a latency of two clock cycles and controls the output buffers like
an output enable. In Write mode, DQM has a latency of zero and
operates as a word mask by allowing input data to be written if it
is low but blocks the write operation if DQM is high.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB39S16400CT-8 | 16 MBit Synchronous DRAM |
| HYB39S16800CT-8 | 16 MBit Synchronous DRAM |
| HYB39S16400BT-10 | JOYSTICK, POTENTIOMETER, 3 AXIS; Angle:20(degree); Centres, fixing:32.2mm; Depth, external:41.5mm; Diameter, panel cut-out:39mm; Length / Height, external:73mm; Material:ABS; Operations, mechanical No. of:1000000; Power, DC:0.125W; RoHS Compliant: Yes |
| HYB39S16400CT-10 | 16 MBit Synchronous DRAM |
| HYB39S16800CT-10 | 16 MBit Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB39S16400AT-10 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
| HYB39S16400AT-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
| HYB39S16400BT-10 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
| HYB39S16400BT-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
| HYB39S16400CT-10 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
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