參數(shù)資料
型號: HYB5117400BJ-60
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 4M x 4-Bit Dynamic RAM 2k & 4k Refresh
中文描述: 4M X 4 FAST PAGE DRAM, 60 ns, PDSO26
封裝: 0.300 INCH, PLASTIC, SO-26
文件頁數(shù): 8/26頁
文件大小: 138K
代理商: HYB5117400BJ-60
HYB 5116(7)400BJ-50/-60
HYB 3116(7)400BJ/BT-50/-60
4M
×
4 DRAM
Semiconductor Group
8
1998-10-01
Capacitance
T
A
= 0 to 70
°
C,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A11)
C
I1
C
I2
C
IO
5
pF
Input capacitance (RAS, CAS, WE, OE)
7
pF
I/O capacitance (I/O1 - I/O4)
7
pF
AC Characteristics
T
A
= 0 to 70
°
C,
V
CC
= 5 V
±
10 % /
V
CC
= 3.3 V
±
0.3 V,
t
T
= 5 ns
Parameter
5, 6
Symbol
Limit Values
Unit Note
-50
-60
min.
max. min.
max.
Common Parameters
Random read or write cycle time
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
T
t
REF
t
REF
90
110
ns
RAS precharge time
30
40
ns
RAS pulse width
50
10k
60
10k
ns
CAS pulse width
13
10k
15
10k
ns
Row address setup time
0
0
ns
Row address hold time
8
10
ns
Column address setup time
0
0
ns
Column address hold time
10
15
ns
RAS to CAS delay time
18
37
20
45
RAS to column address delay time
13
25
15
30
ns
RAS hold time
13
15
ns
CAS hold time
50
60
ns
CAS to RAS precharge time
5
5
ns
Transition time (rise and fall)
3
50
3
50
ns
7
Refresh period for 2k refresh version
32
32
ms
Refresh period for 4k refresh version
64
64
ms
Read Cycle
Access time from RAS
t
RAC
t
CAC
t
AA
50
60
ns
8, 9
Access time from CAS
13
15
ns
8, 9
Access time from column address
25
30
ns
8, 10
相關(guān)PDF資料
PDF描述
HYB 3116400BJ-50 4M×4-Bit Dynamic RAM(4M×4位 動態(tài) RAM)
HYB 3116400BJ-60 4M×4-Bit Dynamic RAM(4M×4位 動態(tài) RAM)
HYB 3117400BJ-50 4M×4-Bit Dynamic RAM(4M×4位 動態(tài) RAM)
HYB 3117400BJ-60 4M×4-Bit Dynamic RAM(4M×4位 動態(tài) RAM)
HYB 5116400BJ-50 4M×4-Bit Dynamic RAM(4M×4位 動態(tài) RAM)
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參數(shù)描述
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