參數(shù)資料
型號: HYB5118160BSJ-50-
廠商: SIEMENS AG
英文描述: 1M x 16-Bit Dynamic RAM 1k Refresh
中文描述: 100萬× 16位動(dòng)態(tài)隨機(jī)存儲(chǔ)器經(jīng)銷商刷新
文件頁數(shù): 7/24頁
文件大小: 191K
代理商: HYB5118160BSJ-50-
HYB 5118160BSJ-50/-60
HYB 3118160BSJ-50/-60
1M
×
16 DRAM
Semiconductor Group
7
1998-10-01
Capacitance
T
A
= 0 to 70
°
C,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A11)
C
I1
C
I2
C
IO
5
pF
Input capacitance (RAS, UCAS, LCAS, WE, OE)
7
pF
I/O capacitance (I/O1 - I/O16)
7
pF
AC Characteristics
T
A
= 0 to 70
°
C,
V
CC
= 5 V
±
10 % /
V
CC
= 3.3 V
±
0.3 V,
t
T
= 5 ns
Parameter
5, 6
Symbol
Limit Values
Unit Note
-50
-60
min.
max. min.
max.
Common Parameters
Random read or write cycle time
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
T
t
REF
90
110
ns
RAS precharge time
30
40
ns
RAS pulse width
50
10k
60
10k
ns
CAS pulse width
13
10k
15
10k
ns
Row address setup time
0
0
ns
Row address hold time
8
10
ns
Column address setup time
0
0
ns
Column address hold time
10
15
ns
RAS to CAS delay time
18
37
20
45
RAS to column address delay time
13
25
15
30
ns
RAS hold time
13
15
ns
CAS hold time
50
60
ns
CAS to RAS precharge time
5
5
ns
Transition time (rise and fall)
3
50
3
50
ns
7
Refresh period for 1k-refresh version
16
16
ms
Read Cycle
Access time from RAS
t
RAC
t
CAC
t
AA
t
OEA
50
60
ns
8 ,9
Access time from CAS
13
15
ns
8, 9
Access time from column address
25
30
ns
8, 10
OE access time
13
15
ns
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參數(shù)描述
HYB5118160BSJ-60 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k Refresh
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