參數(shù)資料
型號: HYB514100BJ-50
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 4M x 1-Bit Dynamic RAM
中文描述: 4M X 1 FAST PAGE DRAM, 50 ns, PDSO20
封裝: 0.300 INCH, PLASTIC, SOJ-26
文件頁數(shù): 6/21頁
文件大?。?/td> 108K
代理商: HYB514100BJ-50
HYB 514100BJ-50/-60
4M
×
1 DRAM
Semiconductor Group
6
1998-10-01
CAS to RAS precharge time
t
CRP
t
T
t
REF
5
5
ns
Transition time (rise and fall)
3
50
3
50
ns
7
Refresh period
16
16
ms
Read Cycle
Access time from RAS
t
RAC
t
CAC
t
AA
t
RAL
t
RCS
t
RCH
50
60
ns
8, 9
Access time from CAS
13
15
ns
8, 9
Access time from column address
25
30
ns
8, 10
Column addr. to RAS lead time
25
30
ns
Read command setup time
0
0
ns
Read command hold time
Read command hold time referenced to RAS
t
RRH
CAS to output in low–Z
0
0
ns
11
0
0
ns
11
t
CLZ
t
OFF
0
0
ns
8
Output buffer turn-off delay
0
13
0
15
ns
12
Write Cycle
Write command hold time
t
WCH
t
WP
t
WCS
t
RWL
t
CWL
t
DS
t
DH
8
10
ns
Write command pulse width
8
10
ns
Write command setup time
0
0
ns
13
Write command to RAS lead time
13
15
ns
Write command to CAS lead time
13
15
ns
Data setup time
0
0
ns
14
Data hold time
10
10
ns
14
Read-Modify-Write Cycle
Read-write cycle time
t
RWC
t
RWD
t
CWD
t
AWD
115
130
ns
RAS to WE delay time
50
60
ns
13
CAS to WE delay time
13
15
ns
13
Column address to WE delay time
25
30
ns
13
AC Characteristics
(cont’d)
T
A
= 0 to 70
°
C,
V
CC
= 5 V
± 10 %,
t
T
= 5 ns
Parameter
5, 6
Symbol
Limit Values
Unit Note
-50
-60
min. max.
min.
max.
相關(guān)PDF資料
PDF描述
HYB 514100BJ-50 4M × 1-Bit Dynamic RAM(4M × 1位動態(tài)RAM)
HYB514100BJ-50- 4M x 1-Bit Dynamic RAM
HYB514100BJ-60 4M x 1-Bit Dynamic RAM
HYB 514171BJ-50 256k × 16-Bit Dynamic RAM(256k × 16位 動態(tài) RAM)
HYB514171BJ-50 256k x 16-Bit Dynamic RAM
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