參數(shù)資料
型號(hào): HYB514175BJ-60
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 256k x 16-Bit EDO-DRAM
中文描述: 256K X 16 EDO DRAM, 60 ns, PDSO40
封裝: 0.400 INCH, PLASTIC, SOJ-40
文件頁(yè)數(shù): 6/22頁(yè)
文件大?。?/td> 177K
代理商: HYB514175BJ-60
HYB 514175BJ/BJL-50/-55/-60
256k
×
16 EDO-DRAM
Semiconductor Group
6
1998-10-01
Standby
V
CC
supply current
(RAS = LCAS = UCAS = WE =
V
CC
– 0.2 V)
Average
V
CC
supply current during
CAS-before-RAS refresh mode
I
CC5
1
mA
1
-50 version
-55 version
-60 version
I
CC6
200
190
170
mA
2, 4
Capacitance
T
A
= 0 to 70
°
C;
V
CC
= 5 V
±
10 %,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A8)
C
I1
C
I2
C
IO
5
pF
Input capacitance (RAS, UCAS, LCAS, WE, OE)
7
pF
Output capacitance (l/O1 to l/O16)
7
pF
AC Characteristics
5, 6
T
A
= 0 to 70
°
C;
V
SS
= 0 V;
V
CC
= 5 V
±
10 %,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Note
-50
-55
-60
min. max. min. max. min. max.
Common Parameters
Random read or write cycle time
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
89
94
104
ns
RAS precharge time
35
35
40
ns
RAS pulse width
50
10k
55
10k
60
10k
ns
CAS pulse width
8
10k
8
10k
10
10k
ns
Row address setup time
0
0
0
ns
Row address hold time
8
8
10
ns
Column address setup time
0
0
0
ns
Column address hold time
8
8
10
ns
RAS to CAS delay time
12
37
12
43
14
45
ns
RAS to column address delay time
10
25
10
30
12
30
ns
DC Characteristics
(cont’d)
T
A
= 0 to 70
°
C;
V
SS
= 0 V;
V
CC
= 5 V
±
10 %,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
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