參數(shù)資料
型號: HYB514400BJ-80
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 1M x 4-Bit Dynamic RAM Low Power 1M x 4-Bit Dynamic RAM
中文描述: 1M X 4 FAST PAGE DRAM, 80 ns, PDSO20
文件頁數(shù): 6/24頁
文件大?。?/td> 124K
代理商: HYB514400BJ-80
HYB 514400BJ-50/-60
1M
×
4 DRAM
Semiconductor Group
6
1998-10-01
Capacitance
T
A
= 0 to 70
°
C;
V
CC
= 5 V
±
10 %;
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A9)
C
I1
C
I2
C
IO
5
pF
Input capacitance (RAS, CAS, WE, OE)
7
pF
Output capacitance (IO1 to IO4)
7
pF
AC Characteristics
T
A
= 0 to 70
°
C,
V
CC
= 5 V
±
10 %,
t
T
= 5 ns
Parameter
5, 6
Symbol
Limit Values
Unit
Note
-50
-60
min. max. min. max.
Common Parameters
Random read or write cycle time
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
T
t
REF
95
110
ns
RAS precharge time
35
40
ns
RAS pulse width
50
10k
60
10k
ns
CAS pulse width
13
10k
15
10k
ns
Row address setup time
0
0
ns
Row address hold time
8
10
ns
Column address setup time
0
0
ns
Column address hold time
10
15
ns
RAS to CAS delay time
18
37
20
45
RAS to column address delay time
13
25
15
30
ns
RAS hold time
13
15
ns
CAS hold time
50
60
ns
CAS to RAS precharge time
5
5
ns
Transition time (rise and fall)
3
50
3
50
ns
7
Refresh period
16
16
ms
Read Cycle
Access time from RAS
t
RAC
t
CAC
t
AA
t
OEA
50
60
ns
8, 9
Access time from CAS
13
15
ns
8, 9
Access time from column address
25
30
ns
8, 10
OE access time
13
15
ns
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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