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參數(shù)資料
| 型號(hào)： | HYB514400BJ-80 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 1M x 4-Bit Dynamic RAM Low Power 1M x 4-Bit Dynamic RAM |
| 中文描述： | 1M X 4 FAST PAGE DRAM, 80 ns, PDSO20 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 124K |
| 代理商： | HYB514400BJ-80 |
HYB 514400BJ-50/-60
1M
×
4 DRAM
Semiconductor Group
9
1998-10-01
Notes:
1. All voltages are referenced to
V
SS
.
2.
I
CC1
,
I
CC3
,
I
CC4
and
I
CC6
depend on cycle rate.
3.
I
CC1
and
I
CC4
depend on output loading. Specified values are measured with the output open.
4. Address can be changed once or less while RAS =
V
IL
. In the case of
I
CC4
it can be changed once
or less during a fast page mode cycle (
t
PC
).
5. An initial pause of 200
μ
s is required after power-up followed by 8 RAS cycles of which at least
one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using
internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS
cycles are required.
6. AC measurements assume
t
T
= 5 ns.
7.
V
IH (MIN.)
and
V
IL (MAX.)
are reference levels for measuring timing of input signals. Transition times
are also measured between
V
IH
and
V
IL
.
8. Measured with a load equivalent to 2 TTL loads and 100 pF.
9. Operation within the
t
RCD (MAX.)
limit ensures that
t
RAC (MAX.)
can be met.
t
RCD (MAX.)
is specified as
a reference point only: If
t
RCD
is greater than the specified
t
RCD (MAX.)
limit, then access time is
controlled by
t
CAC
.
10.Operation within the
t
RAD (MAX.)
limit ensures that
t
RAC (MAX.)
can be met.
t
RAD (MAX.)
is specified as
a reference point only: If
t
RAD
is greater than the specified
t
RAD (MAX.)
limit, then access time is
controlled by
t
AA
.
11.Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
12.
t
OFF (MAX.)
and
t
OEZ (MAX.)
define the time at which the outputs achieve the open-circuit condition
and are not referenced to output voltage levels.
13.Either
t
DZC
or
t
DZO
must be satisfied.
14.Either
t
CDD
or
t
ODD
must be satisfied.
15.
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPWD
are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only. If
t
WCS
>
t
WCS (MIN.)
, the cycle is an early write cycle
and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if
t
RWD
>
t
RWD
(MIN.)
,
t
CWD
>
t
CWD (MIN.)
,
t
AWD
>
t
AWD (MIN.)
and
t
CPWD
>
t
CPWD (MIN.)
, the cycle is a read-write cycle and
I/O pins will contain data read from the selected cells. If neither of the above sets of conditions
is satisfied, the condition of the I/O pins (at access time) is indeterminate.
16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE
leading edge in read-write cycles.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB514400BJ-BT60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 4-Bit Dynamic RAM Low Power 1M x 4-Bit Dynamic RAM |
| HYB514400BJL-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 4-BIT DYNAMIC RAM LOW POWER 1M x 4-BIT DYNAMIC RAM |
| HYB514400BJL-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 4-BIT DYNAMIC RAM LOW POWER 1M x 4-BIT DYNAMIC RAM |
| HYB514400BJL-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 4-BIT DYNAMIC RAM LOW POWER 1M x 4-BIT DYNAMIC RAM |
| HYB514400BJL-80 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 4-Bit Dynamic RAM Low Power 1M x 4-Bit Dynamic RAM |
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