參數(shù)資料
型號: HYB514405BJL-50
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 1M x 4-Bit Dynamic RAM
中文描述: 1M X 4 EDO DRAM, 50 ns, PDSO20
封裝: 0.300 INCH, PLASTIC, SOJ-20
文件頁數(shù): 6/25頁
文件大?。?/td> 1361K
代理商: HYB514405BJL-50
Semiconductor Group
6
HYB 514405BJ/BLJ-50/-60/-70
1M x 4 EDO - DRAM
Average
V
CC
supply current during
CAS before RAS refresh mode
-50 version
-60 version
-70 version
I
CC6
120
110
100
mA
2)4)
For Low Power Version only:
Battery backup current (average power supply
current in battery backup mode):
(CAS = CAS before RAS cycling or 0.2 V,
WE =
V
CC
– 0.2 V or 0.2 V,
A0 to A10 =
V
CC
– 0.2 V or 0.2 V;
D
I
=
V
CC
– 0.2 V or 0.2 V or open,
t
RC
= 125
μ
s,
t
RAS
=
t
RAS
min = 1
μ
s)
I
CC7
250
μ
A
AC Characteristics
5)6)
T
A
= 0 to 70 C,
V
CC
= 5 V
±
10 %,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
-70
min.
max. min.
max. min.
max.
Common Parameters
Random read or write cycle time
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
89
104
124
ns
RAS precharge time
35
40
50
ns
RAS pulse width
50
10k
60
10k
70
10k
ns
CAS pulse width
8
10k
10
10k
12
10k
ns
Row address setup time
0
0
0
ns
Row address hold time
8
10
10
ns
Column address setup time
0
0
0
ns
Column address hold time
8
10
12
ns
RAS to CAS delay time
12
37
14
45
14
53
ns
RAS to column address delay
time
10
25
12
30
12
35
ns
RAS hold time
t
RSH
13
15
17
ns
DC Characteristics
(cont’d)
T
A
= 0 to 70 C,
V
SS
= 0 V,
V
CC
= 5 V
±
10 %,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
相關(guān)PDF資料
PDF描述
HYB514405BJL-60 1M x 4-Bit Dynamic RAM
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