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參數(shù)資料
| 型號： | HYB514800BJ-80 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 512kx8-Bit Dynamic RAM |
| 中文描述： | 512K X 8 FAST PAGE DRAM, 80 ns, PDSO28 |
| 文件頁數(shù)： | 10/22頁 |
| 文件大?。?/td> | 211K |
| 代理商： | HYB514800BJ-80 |
Semiconductor Group
134
Notes:
1) All voltages are referenced to
V
SS
2)
I
CC1
,
I
CC3
,
I
CC4
and
I
CC6
depend on cycle rate.
3)
I
CC1
,
I
CC4
depend on output loading.
4) An initial pause of 200
μ
s is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
5)
V
(min.) and
V
(max.) are reference levels for measuring timing of input signals. Transition times are also
measured between
V
ih
and
V
il
.
6) Measured with a load equivalent to 2 TTL loads and 100 pF.
7)
t
(max.),
t
(max.) defines the time at which the output achieves the open-circuit conditions and are not
referenced to output voltage levels.
8) Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
9) These parameters are references to the CAS leading edge in early write and to the WRITE leading edge in
read-write cycles.
10)
t
WCS
,
t
RWD
,
t
CWD
and
t
AWD
are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only.
If
t
WCS
>
t
WCS
(min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance)
through the entire cycle; if
t
RWD
>
t
RWD
(min.),
t
CWD
>
t
CWD
(min.) and
t
AWD
>
t
AWD
(min.), the cycle is a read-
write cycle and
I/
O will contain data read from the selected cell. If neither of the above sets of conditions is
satisfied, the condition of
I
/O (at access time) is indeterminate.
11) Operation within the
t
RCD
(max.) limit ensure that
t
RAC
(max.) can be met.
t
RCD
(max.) is specified as a
reference point only. If
RAD
is greater than the specified
t
RCD
(max.) limit, then access time is controlled by
t
CAC
.
12) Operation within the
t
RAD
(max.) limit ensured that
t
RAC
(max.) can be met.
t
(max.) is specified as a
reference point only. If
t
RAD
is greater than the specified
RAD
(max.) limit, then access time is controlled by
t
AA
.
13) AC measurements assume
t
T
= 5 ns.
14) Either
t
DZC
or
t
DZO
must be satisfied.
15) Either
t
CDD
or
t
ODD
must be satisfied.
HYB 514800BJ -60/-70/-80
512k x 8 DRAM
相關PDF資料 |
PDF描述 |
|---|---|
| HYB514800BJ-70 | 512kx8-Bit Dynamic RAM |
| HYB514800BJ | 512kx8-Bit Dynamic RAM |
| HYB514800BJ-60 | 512kx8-Bit Dynamic RAM |
| HYBRID-1998 | |
| HYBRID-CAPABILITIES | Optoelectronic |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYB514800BJL-60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Fast Page Mode DRAM |
| HYB514800BJL-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Fast Page Mode DRAM |
| HYB514800BJL-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Fast Page Mode DRAM |
| HYB55A05 | 制造商:SEPA 功能描述:FAN 55MM 5VDC |
| HYB55A05 | 制造商:SEPA 功能描述:FAN 55MM 5VDC |
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