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參數(shù)資料
| 型號： | HYE18P16161ACL85 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16M Asynchronous/Page CellularRAM |
| 中文描述： | 1,600異步/頁的CellularRAM |
| 文件頁數(shù)： | 11/33頁 |
| 文件大?。?/td> | 641K |
| 代理商： | HYE18P16161ACL85 |
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Data Sheet
11
V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85
16M Asynch/Page CellularRAM
Overview
1.4
HYE18P16161AC(-/L)70/85 Ball Definition and Description
Table 2
Ball
CS1
Ball Description - HYE18P16161AC(-/L)70/85
Type
Detailed Function
Input
Chip Select
CS1 enables the command decoder when low and disables it when high. When the
command decoder is disabled new commands are ignored, addresses are don’t care and
outputs are forced to high-Z. Internal operations, however, continue. For the details
please refer to the command tables in
Chapter 1.6
.
Input
Output Enable
OE controls DQ output driver. OE low drives DQ, OE high sets DQ to high-Z.
Input
Write Enable
WE set to low while CS is low initiates a write command.
Input
Upper/Lower Byte Enable
UB enables the upper byte DQ15-8 (resp. LB DQ7 … 0) during read/write operations.
UB (LB) deassertion prevents the upper (lower) byte from being driven during read or
being written.
Input
Deep Power Down Enable/ Set Control Register
Strapping ZZ to low for more than 10μs the device is put to deep power down mode. If a write
access is initiated instantly (<500ns) after ZZ has been asserted to low access to the refresh
configuration register is given. By applying the SET CONTROL REGISTER (SCR) command
(see
Table 3
) the address bus is then loaded into the refresh control register.
Input
Address Inputs
During a Control Register Set operation, the address inputs define the register settings.
I/O
Data Input/Output
The DQ signals 0 to 15 form the 16-bit data bus.
Power
Supply
Power and Ground for the internal logic.
Power
Supply
Isolated Power and Ground for the output buffers to provide improved noise immunity.
–
No Connect
Please do not connect. Reserved for future use, i.e. H6: A20, E3: A21, see ballout in
Figure 2
on
Page 10
.
OE
WE
UB, LB
ZZ
A <19:0>
DQ <15:0>
1
×
V
DD
1
×
V
SS
1
×
V
DDQ
1
×
V
SSQ
2
×
NC
Power Supply, Core
Power Supply, I/O Buffer
相關PDF資料 |
PDF描述 |
|---|---|
| HYE18P16161AC-85 | 16M Asynchronous/Page CellularRAM |
| HYE18P16161AC-60 | MEMORY SPECTRUM |
| HYE18P16161AC-70 | 16M Asynchronous/Page CellularRAM |
| HYE18P32160AC | 32M Synchronous Burst CellularRAM |
| HYE18P32160AC-96 | 32M Synchronous Burst CellularRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYE18P32160AC | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:32M Synchronous Burst CellularRAM |
| HYE18P32160AC-125 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:32M Synchronous Burst CellularRAM |
| HYE18P32160AC-15 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:32M Synchronous Burst CellularRAM |
| HYE18P32160AC-96 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:32M Synchronous Burst CellularRAM |
| HYE18P32160ACL125 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:32M Synchronous Burst CellularRAM |
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