- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370797 > HYM72V1005GU-60 (SIEMENS A G) 3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module PDF資料下載
參數(shù)資料
| 型號： | HYM72V1005GU-60 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module |
| 中文描述： | 1M X 72 EDO DRAM MODULE, 60 ns, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大小： | 74K |
| 代理商： | HYM72V1005GU-60 |
HYM 64(72)V1005GU-50/-60
1M x 64/72 DRAM Module
Semiconductor Group
12
Notes:
1) All voltages are referenced to
V
SS
.
2)
I
CC1
,
I
CC3
,
I
CC4
and
I
CC6
depend on cycle rate.
3)
I
CC1
and
I
CC4
depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during
a hyper page mode (EDO) cycle
5) An initial pause of 200
μ
s is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume
t
T
= 2 ns.
7)
V
(min.)
and
V
are reference levels for measuring timing of input signals. Transition times are also
measured between
V
I
H
and
V
I
L
.
8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined
by the latter of t
RAC
, t
CAC
, t
AA
,t
CPA
,t
OEA
. t
CAC
is measured from tristate.
9) Operation within the
t
limit ensures that
t
RAC (max.)
can be met.
t
RCD (max.)
is specified as a reference point
only. If
t
RCD
is greater than the specified
t
RCD (max.)
t
CAC
.
10) Operation within the
t
)
limit ensures that
t
RAC (max.)
can be met.
t
RAD (max.)
is specified as a reference point
only. If
t
RAD
is greater than the specified
t
RAD (max.)
t
AA
.
11) Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
12)
t
,
t
define the time at which the output achieves the open-circuit conditions and are not
referenced to output voltage levels.
t
OFF
is referenced from the rising edge of RAS or CAS, whichever occurs
last.
13) Either
t
DZC
or
t
DZO
must be satisfied.
14) Either
t
CDD
or
t
ODD
must be satisfied.
15)
t
,
t
,
t
and
t
are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If
t
>
t
, the cycle is an early write cycle and data out pin will remain
open-circuit (high impedance) through the entire cycle; if
t
>
t
,
t
>
t
and
t
>
t
,
the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above
sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.
16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYM72V1600GS-50 | 16M x 72-Bit Dynamic RAM Module |
| HYM72V1610GS-50 | 16M x 72-Bit Dynamic RAM Module |
| HYM72V1600GS-50- | 16M x 72-Bit Dynamic RAM Module |
| HYM72V1610GS-60 | 16M x 72-Bit Dynamic RAM Module |
| HYM72V1600GS-60 | 16M x 72-Bit Dynamic RAM Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYM72V1005GU-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
| HYM72V12C736BLS4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Mx72|3.3V|K/H|x36|SDR SDRAM - Registered DIMM 1GB |
| HYM72V12C736BLS4-H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|128MX72|CMOS|DIMM|168PIN|PLASTIC |
| HYM72V12C736BLS4-K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|128MX72|CMOS|DIMM|168PIN|PLASTIC |
| HYM72V12C736BS4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Mx72|3.3V|K/H|x36|SDR SDRAM - Registered DIMM 1GB |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。