參數(shù)資料
型號: HYM72V1630GS-60
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 16M x 72-Bit Dynamic RAM Module
中文描述: 16M X 72 FAST PAGE DRAM MODULE, 60 ns, DMA168
封裝: DIMM-168
文件頁數(shù): 2/11頁
文件大?。?/td> 69K
代理商: HYM72V1630GS-60
Semiconductor Group
2
HYM72V1620/30GS-50/-60
16M x 72-ECC Module
The HYM 72V1600/10GS-50/-60 is a 128 MByte DRAM module organized as 16 777 216 words by
72-bit in a 168-pin, dual read-out, single-in-line package comprising eighteen HYB 3164400AT/AJ
16M
×
4 DRAMs in 400 mil wide TSOPII or SOJ- packages mounted together with ceramic
decoupling capacitors on a PC board. All inputs except RAS and DQ are buffered by using
BiCMOS buffers/line drivers.
Each HYB 3164400AT/AJ is described in the data sheet and is fully electrically tested and
processed according to Siemens standard quality procedure prior to module assembly. After
assembly onto the board, a further set of electrical tests is performed.
The density and speed of the module can be detected by the use of presence detect pins.
Ordering Information
Pin Names
Presence-Detect and ID-pin Truth Table:
Note:
1 = High Level ( Driver Output) , 0 = Low Level (Driver Output) for PDE active ( ground) . For PDE at a high
level all PD terminal are in tri-state.
Type
Ordering Code
Package
Descriptions
HYM 72V1620GS-50
L-DIM-168-9
3.3V 50ns DRAM module
HYM 72V1620GS-60
HYM 72V1630GS-50
L-DIM-168-9
L-DIM-168-9
3.3V 60ns DRAM module
3.3V 50ns DRAM module
HYM 72V1630GS-60
L-DIM-168-9
3.3V 60ns DRAM module
A0-A12,B0
DQ0 - DQ71
RAS0, RAS2
CAS0 , CAS2
WE0, WE2
OE0, OE2
Vcc
Vss
PD1 - PD8
PDE
ID0 , ID1
N.C.
Address Input
Data Input/Output
Row Address Strobe
Column Address Strobe
Read / Write Input
Output Enable
Power (+3.3 Volt)
Ground
Presence Detect Pins
Presence Detect Enable
ID indentification bit
No Connection
Module
ID0
ID1
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
HYM 72V1620/30GS-50 Vss
Vss
1
1
1
1
0
0
0
0
HYM 72V1620/30GS-60 Vss
Vss
1
1
1
1
0
1
1
0
相關(guān)PDF資料
PDF描述
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