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參數(shù)資料
| 型號： | HYMR212818H |
| 英文描述： | 128Mx18|2.5V|40|x8|Direct RDRAM - 256MB RIMM |
| 中文描述： | 128Mx18 | 2.5V的| 40 | x8 |直接RDRAM的- 256MB的RIMM的 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 291K |
| 代理商： | HYMR212818H |
Rev. 0.95 / J uly.01
4
RIMM
Module
with 256/288Mb RDRAMs Preliminary
TM
Table 3: Module Connector Pad Description
Module Connector Pads
I/O
Signal
Type
Description
A1, A3, A5, A7, A9, A11, A13, A15,
A17, A19, A21, A23, A25, A27, A29,
A31, A33, A39, A52, A60, A62, A64,
A66, A68, A70, A72, A74, A76, A78,
A80, A82, A84, A86, A88, A90, A92,
B1, B3, B5, B7, B9, B11, B13, B15,
B17, B19, B21, B23, B25, B27, B29,
B31, B33, B39, B52, B60, B62, B64,
B66, B68, B70, B72, B74, B76, B78,
B80, B82, B84, B86, B88, B90, B92
Gnd
Ground reference for RDRAM core and interface.
72 PCB connector pads.
B10
I
LCFM
RSL
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Positive polarity
.
B12
I
LCFMN
RSL
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Negative polarity.
B81
I
RCFMN
RSL
Clock from master. Interface clock used for receiv-
ing RSL signals from the Channel. Negative polar-
ity.
B34
I
LCMD
V
CMOS
Serial Command used to read from and write to the
control registers. Also used for power management.
A20, B20, A22, B22, A24
I
LCOL4..
LCOL0
RSL
Column bus. 5-bit bus containing control and address
information for column accesses.
A14
I
LCTM
RSL
Clock to master. Interface clock used for transmit-
ting RSL signals to the Channel. Positive polarity.
A12
I
LCTMN
RSL
Clock to master. Interface clock used for transmit-
ting RSL signals to the Channel. Negative polarity.
A2, B2, A4, B4, A6, B6, A8, B8, A10
I/O
LDQA8..
LDQA0
RSL
Data bus A. A 9-bit bus carrying a byte of read or
write data between the Channel and the RDRAM.
LDQA8 is non-functional on x16 RDRAM devices.
B32, A32, B30, A30, B28, A28, B26,
A26, B24
I/O
LDQB8..
LDQB0
RSL
Data bus B. A 9-bit bus carrying a byte of read or
write data between the Channel and the RDRAM.
LDQB8 is non-functional on x16 RDRAM devices.
B16, A18, B18
I
LROW2..
LROW0
RSL
Row bus. 3-bit bus containing control and address
information for row accesses.
A34
I
LSCK
V
CMOS
Serial Clock input. Clock source used to read from
and write to the RDRAM control registers.
A16, B14, A38, B38, A40, B40, A77,
B79
NC
These pads are not connected. These 8 connector
pads are reserved for future use.
A43, B43, A44, B44, A45, B45, A46,
B46, A47, B47, A48, B48, A49, B49,
A50, B50
NC
These pads are not connected. These 16connector
pads art reserved for future use. The 168 contact
RIMM connector does not connect to these PCB
pads.
B83
I
RCFM
RSL
Clock from master. Interface clock used for receiv-
ing RSL signals from the Channel. Positive polarity.
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