參數(shù)資料
型號(hào): HYS 64V32220GD(L)-8A
廠商: SIEMENS AG
英文描述: 3.3V SDRAM Modules(3.3V SDRAM 模塊)
中文描述: 3.3V的內(nèi)存模塊(3.3V的內(nèi)存模塊)
文件頁(yè)數(shù): 10/12頁(yè)
文件大?。?/td> 90K
代理商: HYS 64V32220GD(L)-8A
HYS64V32220GD(L)-8A
PC100 144 pin SO-DIMM SDRAM Modules
INFINEON Technologies
10
Serial Presence Detects:
A serial presence detect storage device - E
2
PROM - is assembled onto the module. Information about the module
configuration, speed, etc. is written into the E
2
PROM device during module production using a serial presence
detect protocol ( I
2
C synchronous 2-wire bus)
SPD-Table:
Byte#
Description
SPD Entry
Value
Hex
32Mx64
-8A
80
08
04
0D
0
1
2
3
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses
(without BS)
Number of Column Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access time from Clock at
CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
128
256
SDRAM
4
5
6
7
8
9
09
02
40
00
01
A0
60
2
64
0
LVTTL
10.0 ns
6.0 ns
10
11
12
none
00
82
Self-Refresh,
7.8
μ
s
13
14
15
SDRAM width, Primary
Error Checking SDRAM data width
Minimum clock delay for back-to-
back random column address
Burst Length supported
Number of SDRAM banks
Supported CAS Latencies
CS Latencies
WE Latencies
10
00
01
n/a / x8
t
ccd
= 1 CLK
16
17
18
19
20
1, 2, 4 & 8
2
2, & 3
CS latency = 0
Write latency =
0
non buffered/
non reg.
Vcc tol +/-
10%
12.0 ns
6.0 ns
0F
04
06
01
01
21
SDRAM DIMM module attributes
00
22
SDRAM Device Attributes :General
0E
23
24
SDRAM Cycle Time at CL = 2
SDRAM Access Time from Clock at
CL=2
SDRAM Cycle Time at CL = 1
SDRAM Access Time from Clock at
CL=1
Minimum Row Precharge Time
F0
60
25
26
not supported
not supported
FF
FF
27
20 ns
14
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