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參數資料
| 型號： | HYS 72V32300GU |
| 廠商： | SIEMENS AG |
| 英文描述： | 3.3 V 32M × 72-Bit SDRAM Module(3.3 V 32M × 72位 同步動態(tài)RAM模塊) |
| 中文描述： | 3.3伏32M的× 72位SDRAM模塊（3.3伏32M的× 72位同步動態(tài)內存模塊） |
| 文件頁數： | 12/17頁 |
| 文件大?。?/td> | 114K |
| 代理商： | HYS 72V32300GU |
HYS 64/72V32300GU
SDRAM-Modules
Data Book
12
3.00
Notes
1. All AC characteristics are shown for device level.
An initial pause of 100
μ
s is required after power-up. Then a Precharge All Banks command must
be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation
can begin.
2. AC timing tests have
V
IL
= 0.4 V and
V
IH
= 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between
V
IH
and
V
IL
. All AC measurements assume
t
T
= 1 ns with the AC output load circuit shown in Figure below. Specified
t
AC
and
t
OH
parameters
are measured with a 50 pF only, without any resistive termination and with a input signal of 1V/
ns edge rate between 0.8 V and 2.0 V.
3. If clock rising time is longer than 1 ns, a time (
t
T
/2
0.5) ns must be added to this parameter.
4. Rated at 1.4 V.
5. If
t
T
is longer than 1 ns, a time (
t
T
1) ns must be added to this parameter.
6. Whenever the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up” the device.
7. Timing is a asynchronous. If setup time is not met by rising edge of the clock then the CKE signal
is assumed latched on the next cycle.
8. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to
t
RC
is satisfied
after the Self Refresh Exit command is registered.
9. This is referenced to the time at which the output achieved the open circuit condition, not to
output voltage levels.
Note: *)
256MByte PC133 modules with place code “-C” indicating Rev. C dies are used as memory
components are fully PC100 2-2-2 backwards compatible, where PC133 modules with place code
“-A” operates as PC100 3-2-2 on a 100 Mhz memory bus.
A serial presence detect storage device - E
2
PROM - is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E
2
PROM device during module
production using a serial presence detect protocol (I
2
C synchronous 2-wire bus).
50 pF
I/O
Measurement conditions for
t
AC
and
t
OH
SPT03404
CLOCK
2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HYS72V32300GU-7.5-C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HYS72V32300GU-7.5-D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|32MX72|CMOS|DIMM|168PIN|PLASTIC |
| HYS72V32300GU-75-C2 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3 V 32M x 64/72-Bit, 256MByte SDRAM Modules 168-pin Unbuffered DIMM Modules |
| HYS72V32300GU-75-D | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3 V 32M x 64/72-Bit, 256MByte SDRAM Modules 168-pin Unbuffered DIMM Modules |
| HYS72V32300GU-7-D | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3 V 32M x 64/72-Bit, 256MByte SDRAM Modules 168-pin Unbuffered DIMM Modules |
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