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參數(shù)資料
| 型號： | HYS 72V32300GU |
| 廠商： | SIEMENS AG |
| 英文描述： | 3.3 V 32M × 72-Bit SDRAM Module(3.3 V 32M × 72位 同步動態(tài)RAM模塊) |
| 中文描述： | 3.3伏32M的× 72位SDRAM模塊（3.3伏32M的× 72位同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 13/17頁 |
| 文件大小： | 114K |
| 代理商： | HYS 72V32300GU |
HYS 64/72V32300GU
SDRAM-Modules
Data Book
13
3.00
SPD-Table for PC133 Modules
Byte#
Description
SPD Entry Value
Hex
32M
×
64
-7.5
80
08
04
0D
0A
01
40
00
01
75
54
00
82
08
00
01
32M
×
72
-7.5
80
08
04
0D
0A
01
48
00
01
75
54
02
82
08
08
01
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
Number of Row Addresses (without BS bits) 13
Number of Column Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL = 3
SDRAM Access Time from Clock at CL = 3
DIMM Config
Refresh Rate/Type
SDRAM Width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay for Back-to-Back
Random Column Address
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Min. Clock Cycle Time at CAS Latency = 2
for HYS64/72V32300GU-7.5-A
Min. Clock Cycle Time at CAS Latency = 2
for HYS64/72V32300GU-7.5-C
Max. Data Access Time from Clock for
CL = 2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from Clock at
CL = 1
Minimum Row Precharge Time
Minimum Row Active to Row Active Delay
t
RRD
Minimum RAS to CAS Delay
t
RCD
Minimum RAS Pulse Width
t
RAS
Module Bank Density (per bank)
SDRAM Input Setup Time
128
256
SDRAM
10
1
64/72
0
LVTTL
7.5 ns
5.4 ns
none/ECC
Self-Refresh, 7.8
μ
s
x8
n/a/x8
t
CCD
= 1 CLK
16
17
18
19
20
21
22
23
1, 2, 4 & 8
4
CAS latency = 2 & 3
CS latency = 0
Write latency = 0
non buffered/non reg. 00
V
DD
tol +/– 10%
12.0 ns
0F
04
06
01
01
0F
04
06
01
01
00
0E
C0
0E
C0
10.0 ns
A0
A0
24
6.0 ns
60
60
25
26
not supported
not supported
FF
FF
FF
FF
27
28
20 ns
15 ns
14
0F
14
0F
29
30
31
32
20 ns
45 ns
256 MByte
1.5 ns
14
2D
40
15
14
2D
40
15
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72V32300GU-7.5-C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HYS72V32300GU-7.5-D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|32MX72|CMOS|DIMM|168PIN|PLASTIC |
| HYS72V32300GU-75-C2 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3 V 32M x 64/72-Bit, 256MByte SDRAM Modules 168-pin Unbuffered DIMM Modules |
| HYS72V32300GU-75-D | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3 V 32M x 64/72-Bit, 256MByte SDRAM Modules 168-pin Unbuffered DIMM Modules |
| HYS72V32300GU-7-D | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3 V 32M x 64/72-Bit, 256MByte SDRAM Modules 168-pin Unbuffered DIMM Modules |
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