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參數資料
| 型號： | HYS64D16020GDL-8-A |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Unbuffered DDR SDRAM SO Modules |
| 中文描述： | 無緩沖DDR SDRAM的蘇模塊 |
| 文件頁數： | 17/22頁 |
| 文件大?。?/td> | 963K |
| 代理商： | HYS64D16020GDL-8-A |
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Electrical Characteristics
Data Sheet
17
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
Write preamble
t
WPRE
0.2
5
1.1
—
0.25
—
t
CK
2)3)4)5)
Address and control input setup time
t
IS
—
0.9
—
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Address and control input hold time
t
IH
1.1
—
0.9
—
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Read preamble
t
RPRE
t
RPRE1.5
t
RPRES
t
RPST
0.9
0.9
1.5
0.4
0
50
70
1.1
1.1
—
0.60
0.9
NA
NA
0.40
1.1
t
CK
t
CK
ns
t
CK
CL > 1.5
2)3)4)5)
CL = 1.5
2)3)4)5)11)
2)3)4)5)12)
Read preamble setup time
Read postamble
0.60
2)3)4)5)
Active to Precharge command
Active to Active/Auto-refresh command
period
Auto-refresh to Active/Auto-refresh
command period
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command delay
t
RAS
t
RC
120E+3
—
45
65
120E+3 ns
—
2)3)4)5)
ns
2)3)4)5)
t
RFC
80
—
75
—
ns
2)3)4)5)
t
RCD
t
RP
t
RAP
t
RRD
20
20
20
15
—
—
—
—
20
20
20
15
—
—
—
—
ns
ns
ns
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
t
WR
t
DAL
15
—
15
—
ns
t
CK
2)3)4)5)
(
t
wr
/
t
CK
) + (
t
rp
/
t
CK
)
2)3)4)5)13)
t
WTR
t
WTR1.5
t
XSNR
t
XSRD
t
REFI
1
2
80
200 —
—
—
—
—
1
—
75
200
—
—
—
—
—
7.8
t
CK
t
CK
ns
t
CK
μ
s
CL > 1.5
2)3)4)5)
CL = 1.5
2)3)4)5)
2)3)4)5)
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
2)3)4)5)
7.8
2)3)4)5)14)
1) 0
°
C
≤
T
A
≤
70
°
C;
V
DDQ
= 2.5 V
±
0.2 V,
V
DD
= +2.5 V
±
0.2 V
2) Input slew rate
≥
1 V/ns for DDR266, and = 1 V/ns for DDR200
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is
V
REF
. CK/CK slew rate are
≥
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
Table 10
Parameter
AC Timing - Absolute Specifications –8/–7
Symbol
–8
–7
Unit
Note/
Test Condition
1)
DDR200
Min
.
DDR266A
Min.
Max.
Max.
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