參數(shù)資料
型號： HYS64T128021GDL-5-A
廠商： INFINEON TECHNOLOGIES AG
英文描述： 200-Pin Small Outline Dual-In-Line Memory Module
中文描述： 200引腳小外型雙列內(nèi)存模組
文件頁數(shù)： 19/48頁
文件大?。?/td> 1168K
代理商： HYS64T128021GDL-5-A
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
I
DD
Specifications and Conditions
Data Sheet
19
Rev. 0.91, 2004-06
09122003-FTXN-KM26
4
I
DD
Specifications and Conditions
Table 12
Parameter
Operating Current 0
One bank Active - Precharge;
t
CK
=
t
CKmin.
,
t
RC
=
t
RCmin
.,
t
RAS
=
t
RASmin.
, CKE is HIGH, CS is high between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING
.
Operating Current 1
One bank Active - Read - Precharge;
I
OUT
= 0 mA, BL = 4,
t
CK
=
t
CKmin.
,
t
RC
=
t
RCmin
.,
t
RAS
=
t
RASmin.
,
t
RCD
=
t
RCDmin.
,AL = 0, CL = CL
min
.; CKE is HIGH, CS is high between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING
.
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK
=
t
CKmin.
; Other control and address inputs are
SWITCHING, Data bus inputs are SWITCHING.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK
=
t
CKmin.
; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Power-Down Current
All banks open;
t
CK
=
t
CKmin.
, CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit);
Active Power-Down Current
All banks open;
tCK
=
t
CKmin.
, CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit);
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
min.
;
t
CK
=
t
CKmin
.;
t
RAS
=
t
RASmax.
,
t
RP
=
t
RPmin.
; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
I
OUT
= 0 mA.
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
min.
;
t
CK
=
t
CKmin.
;
t
RAS
=
t
RASmax.
,
t
RP
=
t
RPmin.
; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
I
OUT
= 0 mA.
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
min.
;
t
CK
=
t
CKmin.
;
t
RAS
=
t
RASmax.
,
t
RP
=
t
RPmin.
; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
t
CK
=
t
CKmin
., Refresh command every
t
RFC
=
t
RFCmin.
interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Refresh Current
t
CK
=
t
CKmin.
, Refresh command every
t
RFC
=
t
REFI
interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
I
DD
Measurement Conditions
1)2)
Symbol
I
DD0
I
DD1
I
DD2P
I
DD2N
I
DD2Q
I
DD3P(0)
I
DD3P(1)
I
DD3N
I
DD4R
I
DD4W
I
DD5B
I
DD5D
相關(guān)PDF資料
PDF描述
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