參數(shù)資料
型號(hào)： HYS64T128021GDL-5-A
廠商： INFINEON TECHNOLOGIES AG
英文描述： 200-Pin Small Outline Dual-In-Line Memory Module
中文描述： 200引腳小外型雙列內(nèi)存模組
文件頁(yè)數(shù)： 22/48頁(yè)
文件大?。?/td> 1168K
代理商： HYS64T128021GDL-5-A
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
I
DD
Specifications and Conditions
Data Sheet
22
Rev. 0.91, 2004-06
09122003-FTXN-KM26
4.1
I
DD
Test Conditions
For testing the IDD parameters, the timing parameters as in
Table 15
are used.
4.2
ODT (On Die Termination) Current
The ODT function adds additional current consumption
to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A[6,2] in the EMRS(1) a
“weak” or “strong” termination can be selected. The
current consumption for any terminated input pin,
depends on the input pin is in tri-state or driving “0” or
“1”, as long a ODT is enabled during a given period of
time.
Note:For power consumption calculations the ODT duty cycle has to be taken into account
Table 15
Parameter
I
DD
Measurement Test Condition
Symbol
-3.7
PC2-4200-4-4-4
4
3.75
15
60
-5
PC2-3200-3-3-3
3
5
15
55
Unit
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh command
period
Active bank A to Active bank B command
delay
Active to Precharge Command
CL
min
t
CKmin
t
RCDmin
t
RCmin
t
CK
ns
ns
ns
t
RRDmin
10
10
ns
t
RASmin
t
RASmax
t
RPmin
t
RFCmin
45
70000
15
105
40
70000
15
105
ns
ns
ns
ns
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh
command period
Average periodic Refresh interval
t
REFI
7.8
7.8
μ
s
Table 16
Parameter
Enabled ODT current per DQ
ODT is HIGH; Data Bus inputs are FLOATING
ODT current per terminated pin
Symbol
I
ODTO
Min.
5
2.5
10
5
Typ.
6
3
12
6
Max.
7.5
3.75
15
7.5
Unit
mA/DQ
mA/DQ
mA/DQ
mA/DQ
EMRS(1) State
A6 = 0, A2 = 1
A6 = 1, A2 = 0
A6 = 0, A2 = 1
A6 = 1, A2 = 0
Active ODT current per DQ
ODT is HIGH; worst case of Data Bus inputs are
STABLE or SWITCHING.
I
ODTT
相關(guān)PDF資料
PDF描述
HYS64T128021HDL 200-Pin Small Outline Dual-In-Line Memory Module
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