參數(shù)資料
型號: HYS72D64020GU-8-B
廠商: INFINEON TECHNOLOGIES AG
英文描述: 184-Pin Unbuffered Dual-In-Line Memory Modules
中文描述: 184引腳緩沖雙列內(nèi)存模組
文件頁數(shù): 18/51頁
文件大?。?/td> 1356K
代理商: HYS72D64020GU-8-B
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Data Sheet
18
V1.1, 2003-07
Table 9
Parameter
DC Operating Conditions (SSTL_2 Inputs)
Symbol
Values
Unit
Note/ Test Condition
1)
1)
V
DDQ
= 2.5 V,
T
A
= 70
°
C, Voltage Referenced to
V
SS
2) The relationship between the
V
DDQ
of the driving device and the
V
REF
of the receiving device is what determines noise
margins. However, in the case of
V
IH (max.)
(input overdrive), it is the
V
DDQ
of the receiving device that is referenced. In the
case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2 outputs (such as a translator),
and therefore no
V
DDQ
supply voltage connection, inputs must tolerate input overdrive to 3.0 V (High corner
V
DDQ
+ 300 mV).
3) For any pin under test input of 0 V
V
IN
V
DDQ
+ 0.3 V. Values are shown per DDR SDRAM component
min.
V
REF
+ 0.15
– 0.30
– 5
– 5
max.
V
DDQ
+ 0.3
V
REF
– 0.15
5
5
DC Input Logic High
DC Input Logic Low
Input Leakage Current
Output Leakage Current
V
IH (DC)
V
IL (DC)
I
IL
I
OL
V
V
μ
A
μ
A
2)
3)
3)
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