參數(shù)資料
型號(hào)： HYS72D64020GU-8-B
廠商： INFINEON TECHNOLOGIES AG
英文描述： 184-Pin Unbuffered Dual-In-Line Memory Modules
中文描述： 184引腳緩沖雙列內(nèi)存模組
文件頁(yè)數(shù)： 26/51頁(yè)
文件大?。?/td> 1356K
代理商： HYS72D64020GU-8-B
0.45
0.45
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Data Sheet
26
V1.1, 2003-07
7)
t
HZ
and
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
t
DQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate
≥
1.0 V/ns , slow slew rate
≥
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between
V
OH(ac)
and
V
OL(ac)
.
11) CAS Latency 1.5 operation is supported on DDR200 devices only
12)
t
RPRES
is defined for CL = 1.5 operation only
13) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
is equal to the actual system clock
cycle time.
14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 16
Parameter
AC Timing - Absolute Specifications –6/–5
Symbol
–6
–5
Unit
Note/
Test Condition
1)
DDR333
Min.
–0.7
–0.6
DDR400B
Min.
–0.6
–0.5
0.45
0.45
min. (
t
CL
,
t
CH
)
5
6
7.5
0.4
0.4
tbd
Max.
+0.7
+0.6
0.55
0.55
Max.
+0.6
+0.5
0.55
0.55
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
t
AC
t
DQSCK
t
CH
t
CL
t
HP
t
CK
ns
ns
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
min. (
t
CL
,
t
CH
)
6
6
7.5
0.45
0.45
2.2
2)3)4)5)
12
12
12
—
—
—
12
12
12
—
—
—
CL = 3.0
2)3)4)5)
CL = 2.5
2)3)4)5)
CL = 2.0
2)3)4)5)
2)3)4)5)
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width (each
input)
DQ and DM input pulse width (each input)
Data-out high-impedance time from CK/CK
t
HZ
Data-out low-impedance time from CK/CK
Write command to 1
st
DQS latching
transition
DQS-DQ skew (DQS and associated DQ
signals)
t
DH
t
DS
t
IPW
2)3)4)5)
2)3)4)5)6)
t
DIPW
1.75
–0.7
–0.7
0.75
—
+0.7
+0.7
1.25
tbd
–0.6
–0.6
0.75
—
+0.6
+0.6
1.25
ns
ns
ns
t
CK
2)3)4)5)6)
2)3)4)5)7)
t
LZ
t
DQSS
2)3)4)5)7)
2)3)4)5)
t
DQSQ
—
—
—
—
t
HP
–
t
QHS
0.35
+0.40
+0.45
+0.50
+0.55 —
—
—
—
—
+0.40
+0.40
+0.50
+0.50
—
ns
ns
ns
ns
ns
TFBGA
2)3)4)5)
TSOPII
2)3)4)5)
TFBGA
2)3)4)5)
TSOPII
2)3)4)5)
2)3)4)5)
Data hold skew factor
t
QHS
DQ/DQS output hold time
t
QH
t
HP
–
t
QHS
0.35
DQS input low (high) pulse width (write
cycle)
t
DQSL,H
—
—
t
CK
2)3)4)5)
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