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參數(shù)資料
| 型號： | HYS72T64001GR-5-A |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | DDR2 Registered DIMM Modules |
| 中文描述： | 注冊的DDR2內(nèi)存模組 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 725K |
| 代理商： | HYS72T64001GR-5-A |
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
INFINEON Technologies
11
2.04
3.0 Absolute Maximum Ratings
3.1 Operating Temperature Range
3.2 Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Limit Values
Unit
min.
max.
Voltage on any pins relative to V
SS
Voltage on V
DD
relative to V
SS
Voltage on V
DD Q
relative to V
SS
Storage temperature range
V
IN,
V
OUT
V
DD
V
DDQ
T
STG
– 0.5
2.3
V
– 1.0
2.3
V
– 0.5
2.3
-55
+100
o
C
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
Parameter
Symbol
Limit Values
Unit
Notes
min.
max.
DIMM Module Operating Temperature Range (ambient)
TOPR
0
+55
o
C
DRAM Component Case Temperature Range
TCASE
0
+95
o
C
1 - 4
1. DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For
measurement conditions, please refer to the JEDEC document JESD51-2.
2. Within the DRAM Component Case Temperature range all DRAM specification will be supported.
3. Above 85
o
C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 μs.
4. Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below
85
o
C case temperature before initiating self-refresh operation.
Parameter
Symbol
Limit Values
Unit
Notes
min.
nom.
max.
Device Supply Voltage
V
DD
V
DDQ
V
REF
V
DDSPD
V
IH (DC)
V
IL (DC)
I
L
1.7
1.8
1.9
V
-
Output Supply Voltage
1.7
1.8
1.9
V
1)
Input Reference Voltage
0.49 x
V
DDQ
1.7
0.5 x
V
DDQ
–
0.51 x
V
DDQ
3.6
V
2)
EEPROM Supply Voltage
V
DC Input Logic High
V
REF
+ 0.125
– 0.30
–
V
DDQ
+ 0.3
V
REF
– 0.125
5
V
DC Input Logic Low
–
V
In / Output Leakage Current
– 5
–
μ
A
3)
1
2
3
Under all conditions,
V
must be less than or equal to
V
DD
Peak to peak AC noise on
V
may not exceed ± 2%
V
REF (DC)
.
V
REF
is also expected to track noise variations in
V
DDQ
.
For any pin on the DIMM connector under test input of 0 V
V
IN
≤
V
DDQ
+ 0.3 V.
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