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| 型號(hào)： | HYS72T64001GR-5-A |
| 廠(chǎng)商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | DDR2 Registered DIMM Modules |
| 中文描述： | 注冊(cè)的DDR2內(nèi)存模組 |
| 文件頁(yè)數(shù)： | 15/24頁(yè) |
| 文件大?。?/td> | 725K |
| 代理商： | HYS72T64001GR-5-A |
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HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
INFINEON Technologies
15
2.04
4.5 I
DD
Measurement Conditions (cont’d)
For testing the IDD parameters, the following timing parameters are used:
4.5 ODT (On Die Termination) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A6 & A2 in the EMRS(1) a “week” or “strong” termination can be selected. The cur-
rent consumption for any terminated input pin, depends on the input pin is in tri-state or driving “0” or “1”, as long
a ODT is enabled during a given period of time.
ODT current per terminated pin:
Parameter
Symbol
-5
PC2-3200
-3.7
PC2-4200
-3
PC2-5300
Unit
3-3-3
4-4-4
4-4-4
CAS Latency
CL(IDD)
3
4
4
tCK
Clock Cycle Time
tCK(IDD)
5
3.75
3
ns
Active to Read or Write delay
tRCD(IDD)
15
15
12
ns
Active to Active / Auto-Refresh command period
tRC(IDD)
60
60
57
ns
Active bank A to Active bank B command delay
tRRD(IDD)
7.5
7.5
7.5
ns
Active to Precharge Command
tRASmin(IDD)
45
45
45
ns
tRASmax(IDD)
70000
70000
70000
ns
Precharge Command Period
tRP(IDD)
15
15
12
ns
Auto-Refresh to Active / Auto-Refresh command
period
tRFC(IDD)
75
75
75
ns
Average periodic Refresh interval
tREFI
7.8
7.8
7.8
μs
EMRS(1) State
min.
typ.
max.
Unit
Enabled ODT current per DQ
added IDDQ current for ODT enabled;
ODT is HIGH; Data Bus inputs are FLOATING
IODTO
A6 = 0, A2 = 1
5
6
7.5
mA/DQ
A6 = 1, A2 = 0
2.5
3
3.75
mA/DQ
Active ODT current per DQ
added IDDQ current for ODT enabled;
ODT is HIGH; worst case of Data Bus inputs
are STABLE or SWITCHING.
IODTT
A6 = 0, A2 = 1
10
12
15
mA/DQ
A6 = 1, A2 = 0
5
6
7.5
mA/DQ
note: For power consumption calculations the ODT duty cycle has to be taken into account
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