參數(shù)資料
型號(hào)： I843034AY-06
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： 750 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
文件頁(yè)數(shù)： 4/21頁(yè)
文件大?。?/td> 976K
代理商： I843034AY-06
IDT / ICS 3.3V LVPECL FREQUENCY SYNTHESIZER
12
ICS843034AY-06 REV. A MARCH 7, 2007
ICS843034-06
FEMTOCLOCKS MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843034-06 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. V
CC, VCCA, and VCCO_x should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, power supply isolation is
required. Figure 2 illustrates how a 10
Ω resistor along with a
10
μF and a .01μF bypass capacitor should be connected to
each V
CCA pin.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 2. POWER SUPPLY FILTERING
10
Ω
V
CCA
10
μF
.01
μF
3.3V
.01
μF
V
CC
APPLICATION INFORMATION
Figure 3 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS/LVTTL LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VCC
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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