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參數(shù)資料
| 型號： | IBM25403GCX-3JC76C2 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 21/54頁 |
| 文件大?。?/td> | 541K |
| 代理商： | IBM25403GCX-3JC76C2 |
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IBM PowerPC 403GCX
28
Notes:
1. For all output timing, TOH and TOV are relative to the rising edge of SysClk.
2. For detailed EDO DRAM timing waveforms, refer to "EDO DRAM 2-1-1-1 Burst Read Followed by Single Transfer
3. The Address bus, RAS, CAS and DRAMOE output timings (with respect to the falling edge of the internal duty
cycle corrected SysClk) vary with the 403GCX operating frequency. Use the following equations to determine the
worst-case output delay and hold times for these signals: TOVfMax = Tc/2 + TOVrMax; TOHfMin = Tc/2 + TOHrMin,
where TOVrMax and TOHrMin correspond to the specications for the speed grade of the part. Valid for Tc greater
than 25 ns and less than 41.7 ns.
4. In early RAS mode, the RAS output delay varies with the 403GCX operating frequency. Use the following equation
to determine the worst-case output delay for this signal: TOV15Max = Tc/4 + TOH15Min, where TOH15Min corre-
sponds to the specication for the speed grade of the part. TOHMin remains unchanged. Valid for Tc greater than
25 ns and less than 41.7 ns.
5. Parity timings are for DMA buffered mode. For normal memory accesses, use the data bus timings for parity.
6. Output times are measured with a standard 50 pF capacitive load, unless otherwise noted. Output hold times are
measured as TOVmin at 3.47V and Tj=0°C.
7. All output hold and oat times are guaranteed by design and not tested.
8. Noted output valid times guaranteed by design and not tested.
Note:
1. Relationships are guaranteed by design and are not tested. Relationships also assume 50 pF capacitive loading
on interface signals.
2. For detailed DRAM interface timing waveforms, refer to "DRAM Interface Timing Diagram," on page 29.
Table 18. 403GCX DRAM Interface Timing Relationships
Symbol
Parameter
38 MHz
Units
Min
TASR
Row Address Setup Time to RAS:
BRn[ERM] = 0
BRn[ERM] = 1
0.5TC -4.0
0.25TC -2.5
ns
TRAH
Row Address Hold Time:
BRn[ERM] = 0
BRn[ERM] = 1
0.5TC -1.5
0.67TC -0.5
ns
TASC
Column Address Setup Time to CAS
0.5TC -4.0
ns
TCAH
Column Address Hold Time
0.5TC -2.0
ns
TCAS
Available CAS Access Time:
2-1-1-1 access
3-2-2-2 access
3-1-1-1 access
0.5TC -2.5
1.5TC -2.5
0.5TC -2.5
ns
TCP
CAS Precharge Time
0.5TC -2.5
ns
TDS
Write Data Setup Time to CAS
0.5TC -4.0
ns
TRP
RAS Precharge Time:
BRn[ERM] = 0 and BRn[PCC] = 0
BRn[ERM] = 0 and BRn[PCC] = 1
BRn[ERM] = 1 and BRn[PCC] = 0
BRn[ERM] = 1 and BRn[PCC] = 1
1.5TC -2.5
2.5TC -2.5
1.25TC -1.0
2.25TC -1.0
ns
TRAS
RAS Active During Refresh:
BR[RAR] = 0
BR[RAR] = 1
1.5TC -1.5
2.5TC -1.5
ns
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