參數(shù)資料
型號： IBM25EMPPC750EBUB2660
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數(shù)： 10/43頁
文件大?。?/td> 431K
代理商： IBM25EMPPC750EBUB2660
Preliminary and subject to change without notice
PPC740 and PPC750 Hardware Specifications
18 of 43
3.1.3 IEEE 1149.1 AC Timing Specications
Table 13 provides the IEEE 1149.1 (JTAG) AC timing specications as dened in
Figure 9 , Figure 10 , Figure 11 , and Figure 12 . The ve JTAG signals are; TDI, TDO,
TMS, TCK, and TRST.
Notes:
1. TRST is an asynchronous level sensitive signal. Guaranteed by design.
2. Non-JTAG signal input timing with respect to TCK.
3. Non-JTAG signal output timing with respect to TCK.
4. Guaranteed by characterization and not tested.
5. Minimum spec guaranteed by characterization and not tested.
Figure 9 provides the JTAG clock input timing diagram.
Figure 9. JTAG Clock Input Timing Diagram
Table 13. JTAG AC Timing Specications (Independent of SYSCLK)
Operating conditions are specied in Section Table 2., "Recommended Operating Conditions" CL = 50 pF
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
33.3
MHz
1
TCK cycle time
30
—
ns
2
TCK clock pulse width measured at 1.4V
15
—
ns
3
TCK rise and fall times
0
2
ns
4
spec obsolete, intentionally omitted
5
TRST
assert time
25
—
ns
1
6
Boundary-scan input data setup time
4
—
ns
2
7
Boundary-scan input data hold time
15
—
ns
2
8
TCK to output data valid
4
20
ns
3,5
9
TCK to output high impedance
3
19
ns
3,4
10
TMS, TDI data setup time
0
—
ns
11
TMS, TDI data hold time
12
—
ns
12
TCK to TDO data valid
2.5
12
ns
5
13
TCK to TDO high impedance
3
9
ns
4
TCK
VM
1
2
3
VM
VM = Midpoint Voltage (1.4v)
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