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參數(shù)資料
| 型號： | IBM25EMPPC750EBUB2660 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 34/43頁 |
| 文件大?。?/td> | 431K |
| 代理商： | IBM25EMPPC750EBUB2660 |
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Preliminary and subject to change without notice
PPC740 and PPC750 Hardware Specifications
4 of 43
arithmetic
-- 3 cycle latency, 1 cycle throughput, single-precision multiply-add
-- 3 cycle latency, 1 cycle throughput, double-precision add
-- 4 cycle latency, 2 cycle throughput, double-precision multiply-add
-- Hardware support for divide
-- Hardware support for denormalized numbers
-- Time deterministic non-IEEE mode
System unit
-- Executes CR logical instructions and miscellaneous system instructions
-- Special register transfer instructions
Cache structure
-- 32K, 32-byte line, 8-way set associative instruction cache
-- 32K, 32-byte line, 8-way set associative data cache
-- Single-cycle cache access
-- Pseudo-LRU replacement
-- Copy-back or write-through data cache (on a page per page basis)
-- Supports all PowerPC memory coherency modes
-- Non-blocking instruction and data cache (one outstanding miss under hits)
-- No snooping of instruction cache
Memory management unit
-- 128 entry, 2-way set associative instruction TLB
-- 128 entry, 2-way set associative data TLB
-- Hardware reload for TLB's
-- 4 instruction BAT's and 4 data BATs
-- Virtual memory support for up to 4 exabytes (252) virtual memory
-- Real memory support for up to 4 gigabytes (232) of physical memory
Level 2 (L2) cache interface (not included on the PPC740)
-- Internal L2 cache controller and 4K-entry tags; external data SRAMs
-- 256K, 512K, and 1 Mbyte 2-way set associative L2 cache support
-- Copy-back or write-through data cache (on a page basis, or for all L2)
-- 64-byte(256K/512K) and 128-byte (l-Mbyte) sectored line size
-- Supports ow-through (reg-buf) synchronous burst SRAMs, pipelined
(reg-reg) synchronous burst SRAMs, and pipelined (reg-reg) late-write
synchronous burst SRAMs
-- Design supports Core-to-L2 frequency divisors of
÷1, ÷1.5, ÷2, ÷2.5, and ÷3.
However, this specication supports the L2 frequency range specied in
Section 3.1.2.4, “L2 Clock AC Specications“. For higher L2 frequencies not sup-
ported in this document, please contact your IBM marketing representative.
Bus interface
-- Compatible with 60x processor interface
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