參數(shù)資料
型號(hào): IBM25EMPPC750EBUB2660
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數(shù): 12/43頁
文件大?。?/td> 431K
代理商: IBM25EMPPC750EBUB2660
Preliminary and subject to change without notice
PPC740 and PPC750 Hardware Specifications
2 of 43
1.0 Overview
The PPC740 and PPC750 are targeted for high performance, low power systems and
support the following power management features - doze, nap, sleep, and dynamic
power management. The PPC750 consists of a processor core and an internal L2 Tag
combined with a dedicated L2 cache interface and a 60x bus. The PPC740 is the same
design as the PPC750, except that the L2 interface pins are not brought out on the
package. The PPC740 is meant to be run in applications that do not require an L2.
Figure 1 shows a block diagram of the PPC740 and PPC750.
Figure 1. PPC740 and PPC750 Block Diagram
FXU2
GPRs
LSU
FPRs
FPU
Instruction Fetch
System
Completion
Rename
Buffers
Unit
32K ICache
32K DCache
BHT /
BIU
60X
L2 Cache
FXU1
L2 Tags
Dispatch
Branch Unit
BTIC
Control Unit
(Not available
in PPC740)
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