參數(shù)資料
型號(hào): IBM25NPE405L-3FA266CZ
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA324
封裝: 23 X 23 MM, PLASTIC, EBGA-324
文件頁數(shù): 24/52頁
文件大?。?/td> 907K
代理商: IBM25NPE405L-3FA266CZ
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
30
Signal Description
The following table provides a summary of the number of package pins (balls) associated with each functional
interface group.
Multiplexed pins
In the table “Signal Functional Description” on page 32, each external signal is listed along with a short
description of the signal function. The signals are grouped together according to their function. Some signals
are multiplexed on the same package pin (ball) so that the pin can be used for different functions. In most
cases, the signal name is shown in this table unaccompanied by multiplexed signal names that may be
associated with it. In cases where multiplexed signals are in the same functional group, the names appear as
a default signal followed by secondary signals in square brackets (for example, EMC0TxErr[EMC0Tx1En]).
Active-low signals (for example, RAS) are marked with an overline. Any signal that is not the primary (default)
signal on a multiplexed pin is shown in square brackets.
The active signal on a multiplexed pin is controlled by programming. It is expected that in any single
application, a particular pin will always be programmed to serve the same function. The flexibility of
multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible.
Initialization Strapping
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs
only during reset and are used for other functions during normal operation (see “Initialization” on page 51).
Note that the use of these pins for strapping is not considered multiplexing since the strapping function is not
programmable.
Pull-up and Pull-down Resistors
Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in
an appropriate state. The recommended pull-up value of 3k
to +3.3V (10k to +5V can be used on 5V
tolerant I/Os) and pull-down value of 1k
to GND, applies only to individually terminated signals. To prevent
possible damage to the device, I/Os capable of becoming outputs
must never be tied together and terminated
through a common resistor.
If your system-level test methodology permits, input-only signals can be connected together and terminated
through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure
Pin Summary
Group
No. of Pins
Nonmultiplexed Signals
167
Multiplexed Signals
48
Total Signal Pins
215
AVDD
1
OVDD
16
VDD
8
Gnd
48
Gnd (and thermal)
36
Reserved
0
Total Pins
324
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