參數(shù)資料
型號(hào)： IBM25PPC750GLECR5HA3T
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA292
封裝： 21X 21 MM, 1 MM PITCH, CERAMIC, BGA-292
文件頁數(shù)： 42/76頁
文件大?。?/td> 1031K
代理商： IBM25PPC750GLECR5HA3T
Datasheet
IBM PowerPC 750GL RISC Microprocessor
Preliminary
DD1.X
750GL_ds_body.fm 1.2
March 13, 2006
System Design Information
Page 47 of 74
After both PLLs are running and locked, the processor frequency can be toggled with very low latency.
For example, when it is time to change back to the PLL0 frequency, there is no need to wait for PLL lock.
HID1[PS] can be reset to '0', causing the processor clock source to transition from PLL1 back to PLL0. If
PLL0 will not be needed for some time, it can be configured to be off while not in use. This is done by
resetting the HID1[PC0] field to '0', and setting HID1[PI0] to '1'. Turning the non-selected PLL off results
in a modest power savings, but introduces added latency when changing frequency. If PLL0 is configured
to be off, the procedure for switching to PLL0 as the selected PLL involves changing the configuration
and range bits, waiting for lock, and then selecting PLL0, as described in the previous paragraph.
5.1.2 Restrictions and Considerations for PLL Configuration
Consider the following when reconfiguring the PLLs:
The configuration and range bits in HID1 should only be modified for the non-selected PLL, since it will
require time to lock before it can be used as the source for the processor clock.
The HID1[PI0] bit should only be modified when PLL0 is not selected.
Whenever one of the PLLs is reconfigured, it must not be selected as the active PLL until enough time
has elapsed for the PLL to lock.
At all times, the frequency of the processor clock, as determined by the various configuration settings,
must be within the specification range for the current operating conditions.
Never select a PLL that is in the off configuration.
5.1.2.1 Configuration Restriction on Frequency Transitions
It is considered a programming error to switch from one PLL to the other when both are configured in a
half-cycle multiplier mode. For example, with PLL0 configured in 9:2 mode (PC0) and PLL1 configured in
13:2 mode (PC1), changing the select bit (HID1[PS]) is not allowed. In cases where such a pairing of configu-
rations is desired, an intermediate full-cycle configuration must be used between the two half-cycle modes.
For example, with PLL0 at 9:2, PLL1, configured at 6:1, is selected. Then PLL0 is re configured at 13:2,
locked, and selected.
5.1.3 PLL_RNG[0:1] Definitions for Dual PLL Operation
The dual PLLs on the 750GL are configured by the PLL_CFG[0:4] and PLL_RNG[0:1] signals. For a given
SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and voltage controlled oscillator
(VCO) frequency of operation. The 750GL PLL range configuration for dual PLL operation is shown in the
following table.
Table 5-1. PLL_RNG[0:1] Definitions for Dual PLL Operation
PLL_RNG[0:1]
PLL Frequency Range
00 (default)
600 MHz–900 MHz
01 (fast)
900 MHz–1.0 GHz
10 (slow)
500 MHz–600 MHz
11 (reserved)
Reserved
Note: PLL_RNG bit settings are valid for a VDD range of 1.4 V–1.55 V and a temperature range of -40°C–105°C.
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