參數(shù)資料
型號(hào): IC42S16400-7TIG
英文描述: 1M x 16Bit x 4 Banks (64-MBIT) SDRAM
中文描述: 100萬× 16 × 4銀行(64兆位)內(nèi)存
文件頁數(shù): 27/68頁
文件大?。?/td> 1092K
代理商: IC42S16400-7TIG
IC42S16400
Integrated Circuit Solution Inc.
DR034-0E 12/02/2003
27
Precharge Termination in WRITE Cycle
During WRITE cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after t
RP
from the precharge command. The DQM must be high to mask
invalid data in.
During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However, invalid
data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high
at the same clock as the precharge command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
Burst lengh = X
CLK
Command
CAS latency = 2
DQM
Hi - Z
Write
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
RP
PRE
ACT
DQ
Write
PRE
ACT
t
RP
CAS latency = 3
Hi - Z
D0
D3
D2
D1
D0
D3
D2
D1
DQM
D4
D4
command
DQ
相關(guān)PDF資料
PDF描述
IC42S16400 1M x 16Bit x 4 Banks (64-MBIT) SDRAM
IC42S16400-6BG RES 100-OHM 5% 0.1W 200PPM THICK-FILM SMD-0603 5K/REEL-7IN-PA
IC42S16400-6BIG 1M x 16Bit x 4 Banks (64-MBIT) SDRAM
IC42S16400-6T 1M x 16Bit x 4 Banks (64-MBIT) SDRAM
IC42S16400-6TG RES 1K-OHM 1% 0.1W 100PPM THICK-FILM SMD-0603 5K/REEL-7IN-PA
相關(guān)代理商/技術(shù)參數(shù)
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