參數(shù)資料
型號: IC42S16400-7TIG
英文描述: 1M x 16Bit x 4 Banks (64-MBIT) SDRAM
中文描述: 100萬× 16 × 4銀行(64兆位)內(nèi)存
文件頁數(shù): 8/68頁
文件大?。?/td> 1092K
代理商: IC42S16400-7TIG
IC42S16400
8
Integrated Circuit Solution Inc.
DR034-0E 12/02/2003
AC ELECTRICAL CHARACTERISTICS
(At T
A
= 0 ~ 70°C, V
DD
= V
DDQ
= 3.3 ± 0.3V, V
SS
= V
SSQ
= 0V , unless otherwise note
d
)
-6
-7
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
t
CK
3
t
CK
2
t
AC
3
t
AC
2
t
CH
t
CL
t
CKE
t
CKH
t
AS
t
AH
t
CMS
t
CMH
t
DS
t
DH
t
OH
3
t
OH
2
t
LZ
t
HZ
t
RC
t
RAS
t
RCD
t
RP
t
RRD
t
DPL
t
T
t
RSC
t
PDE
t
SRX
t
REF
CLK Cycle Time
CAS
Latency = 3
CAS
Latency = 2
CAS
Latency = 3
CAS
Latency = 2
6
5
6
5
7.5
10
2.5
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2.7
3
0
2.7
67.5
45
20
20
15
15
1
10
7.5
7.5
5.4
6
5.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
7.5
2.5
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2.5
2
.5
0
2.5
60
42
18
15
12
12
1
10
7.5
7.5
CLK to valid output delay
(1)
CLK high pulse width
CLK low pulse width
CKE setup time
CKE hold time
Address setup time
Address hold time
Command setup time
Command hold time
Data input setup time
Data input hold time
Output data hold time
(1)
CAS
Latency = 3
CAS
Latency = 2
CLK to output in low - Z
CLK to output in H - Z
ROW cycle time
ROW active time
RAS
to
CAS
delay
Row precharge time
Row active to active delay
Data in to precharge
Transition time
Mode reg. set cycle
Power down exit setup time
Self refresh exit time
Refresh Time
100,000
10
64
100,000
10
64
Notes:
1.
if clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter.
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PDF描述
IC42S16400 1M x 16Bit x 4 Banks (64-MBIT) SDRAM
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