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參數(shù)資料
| 型號： | ICS1572M-101 |
| 英文描述： | GT 4C 4#12 PIN RECP WALL RM |
| 中文描述： | 用戶可編程的差分輸出圖形時鐘發(fā)生器 |
| 文件頁數(shù)： | 15/19頁 |
| 文件大小： | 276K |
| 代理商： | ICS1572M-101 |
SYMBOL
F
vco
F
xtal
C
par
F
load
T
xhi
T
xlo
T
high
PARAMETER
MIN
20
5
TYP
MAX
160
20
UNITS
MHz
MHz
pF
MHz
ns
ns
%
VCO Frequency (see Note 1)
Crystal Frequency
Crystal Oscillator Loading Capacitance
LOAD Frequency
XTAL1 High Time (when driven externally)
XTAL1 Low TIme (when driven externally)
Differential Clock Output Duty Cycle
(see Note 2)
Differential Clock Output Cumulative
Jitter (see Note 3)
PLL Acquire Time (to within 1%)
VDD Supply Current
VDDO Supply Current (excluding CLK+/-
termination)
20
80
8
8
45
55
J
clk
<0.06
pixel
T
lock
I
dd
I
ddo
500
15
20
μ
s
mA
mA
t.b.d.
t.b.d.
DIGITAL INPUTS - ICS1572-101
1
2
3
4
5
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
STROBE Pulse Width (T
hi
or T
lo
)
10
10
10
10
20
ns
ns
ns
ns
ns
DIGITAL OUTPUTS - ICS1572-301
6
7
8
DATA/HOLD~Setup Time
DATA/HOLD~Hold Time
DATCLK Pulse Width (T
hi
or T
lo
)
10
10
20
ns
ns
ns
PIPELINE DELAY RESET
9
10
11
12
Reset Activation Time
Reset Duration
Restart Delay
Restart Matching
2*Tclk
ns
ns
ns
ns
4*Tload
2*Tload
+1.5*Tclk
-1*Tclk
DIGITAL OUTPUTS
13
14
CLK+/CLK- Clock Rate
LOAD To LD/N2 Skew (Shift Clock Mode)
180
+2
MHz
ns
-2
0
Note 1: Use of the post-divider is required for frequencies lower than 20 MHz on CLK+ & CLK- outputs. Use of the post-divider
is recommended for output frequencies lower than 65 MHz.
Note 2: Using load circuit of Figure 6. Duty cycle measured at zero crossings of difference voltage between CLK+ and CLK-.
Note 3: Cumulative jitter is defined as the maximum error (in the time domain) of any CLK edge, at any point in time, compared
with the equivalent edge generated by an ideal frequency source.
ICS laboratory testing indicates that the typical value shown above can be treated as a maximum jitter specification in
virtually all applications. Jitter performance can depend somewhat on circuit board layout, decoupling, and register
programming.
AC Characteristics
ICS1572
15
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| ICS1574BM | 功能描述:IC CLOCK GEN PROGR LASER 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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