參數(shù)資料
型號: ICS1572M-101
英文描述: GT 4C 4#12 PIN RECP WALL RM
中文描述: 用戶可編程的差分輸出圖形時鐘發(fā)生器
文件頁數(shù): 7/19頁
文件大?。?/td> 276K
代理商: ICS1572M-101
Register Mapping - ICS1572-101 (Parallel Programming Option)
NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1572. PC SOFTWARE IS AVAILABLE
FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS.
REG#
BIT(S)
BIT REF.
DESCRIPTION
0
1
0-3
0-2
R[0]..R[3]
R[4]..R[6]
Reference divider modulus control bits
Modulus = value + 1
2
0-3
A[0]..A[3]
Controls A counter. When set to zero, modulus=7. Otherwise,
modulus=7 for “value” underflows of the prescaler, and modulus=6
thereafter until M counter underflows.
3
4
0-3
0-1
M[0]..M[3]
M[4]..M[5]
M counter control bits
Modulus = value + 1
4
3
DBLFREQ
Doubles modulus of dual-modulus prescaler (from 6/7 to 12/14).
5
0-2
N1[0]..N1[2]
Sets N1 modulus according to this table. These bits are set to imple-
ment a divide-by-four on power-up.
6
7
0-3
0-3
N2[0]..N2[3]
N2[4]..N2[7]
Sets the modulus of the N2 divider. Modulus = value + 1
The input of the N2 divider is the output of the N1 divider in all clock
modes except AUXEN.
8
3
N2[8]
8
0-2
V[0]..V[1]
Sets the gain of the VCO.
N1[2]
0
0
0
0
1
1
1
1
N1[1]
0
0
1
1
0
0
1
1
N1[0]
0
1
0
1
0
1
0
1
RATIO
3
4
4
5
6
8
8
10
V[2]
V[1]
V[0]
VCO GAIN
(MHz/VOLT)
30
45
60
80
1
1
1
1
0
0
1
1
0
1
0
1
ICS1572
7
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