參數(shù)資料
型號： ICS1893BFILF
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 62/133頁
文件大小： 0K
描述： PHYCEIVER LOW PWR 3.3V 48-SSOP
標(biāo)準(zhǔn)包裝： 30
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 48-SSOP
包裝： 管件
其它名稱： 1893BFILF
ICS1893BF, Rev. F, 5/13/10
May, 2010
34
Chapter 6 Functional Blocks
ICS1893BF Data Sheet - Release
Copyright 2009, IDT, Inc.
All rights reserved.
6. To indicate that the auto-negotiation process is complete, the ICS1893BF sets bits 1.5 and 17.4 high to
logic one. After successful completion of the auto-negotiation process, the ICS1893BF
Auto-Negotiation sublayer performs the following steps:
a. It sets to logic one the Status Register’s Auto-Negotiation Complete bit (bit 1.5, which is also
available in the QuickPoll register as bit 17.4).
b. It enables the negotiated link technology (such as the 100Base Transmit modules and 100Base
Receive modules).
c. It disables the unused technologies to reduce the overall power consumption.
6.2.2 Auto-Negotiation: Parallel Detection
The ICS1893BF supports parallel detection. It is therefore compatible with networks that do not support the
auto-negotiation process. When enabled, the Auto-Negotiation sublayer can detect legacy 10Base-T link
partners as well as 100Base-TX link partners that do not have an auto-negotiation capability.
The Auto-Negotiation sublayer performs this parallel detection function when it does not get a response to
its FLP bursts. In these situations, the Auto-Negotiation sublayer performs the following steps:
1. It sets the LP_AutoNeg_Able bit (bit 6.0) to logic zero, thereby identifying the remote link partner as not
being capable of executing the auto-negotiation process.
2. It sets the bit in the Auto-Negotiation Link Partner Abilities Register that corresponds to the 'parallel
detected' technology [for example, half-duplex, 10Base-T (bit 5.5) or half-duplex, 100Base-TX (bit
5.7)].
3. It sets the Status Register’s Auto-Negotiation Complete bit (bit 1.5) to logic one, indicating completion
of the auto-negotiation process.
4. It enables the detected link technology and disables the unused technologies.
A remote link partner that does not support the auto-negotiation process does not respond to the
transmitted FLP bursts. The ICS1893BF detects this situation and responds according to the data it
receives. The ICS1893BF can receive one of five potential responses to the FLP bursts it is transmitting:
FLP bursts, 10Base-T link pulses (that is, Normal Link Pulses), scrambled 100Base IDLEs, nothing, or a
combination of signal types.
A 10Base-T link partner transmits only Normal Link Pulses when idle. When the ICS1893BF receives
Normal Link Pulses, it concludes that the remote link partner is a device that can use only 10Base-T
technology. A 100Base-TX node without an Auto-Negotiation sublayer transmits 100M scrambled IDLE
symbols in response to the FLP bursts. Upon receipt of the scrambled IDLEs, the ICS1893BF concludes
that its remote link partner is a 100Base-TX node that does not support the auto-negotiation process. For
both 10Base-T and 100Base-TX nodes without an Auto-Negotiation sublayer, the ICS1893BF clears bit 6.0
to logic zero, indicating that the link partner cannot perform the auto-negotiation process.
If the remote link partner responds to the FLP bursts with FLP bursts, then the link partner is a 100Base-TX
node that can support the auto-negotiation process. In this case, the ICS1893BF sets to logic one the
Auto-Negotiation Expansion Register’s Link Partner Auto-Negotiation Ability bit (bit 6.0).
If the Auto-Negotiation sublayer does not receive any signal when monitoring the receive channel, then the
QuickPoll Detailed Status Register’s Signal Detect bit (bit 17.3) is set to logic one, indicating that no signal
is present.
Another possibility is that the ICS1893BF senses that it is receiving multiple technology indications. In this
situation, the ICS1893BF cannot determine which technology to enable. It informs the STA of this problem
by setting to logic one the Auto-Negotiation Expansion Register’s Parallel Detection Fault bit (bit 6.4).
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ICS1893BFILFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893BFIT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
ICS1893BFLF 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893BFLFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893BFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
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